公开(公告)号：US20190189561A1

公开(公告)日：2019-06-20

申请号：US16278972

申请日：2019-02-19

申请人： Chip Solutions, LLC

发明人： Sukianto Rusli

IPC分类号： H01L23/538 ,  H01L23/532 ,  H01L23/31 ,  H01L23/528 ,  H01L23/522 ,  H01L21/56 ,  H01L21/768 ,  H01L21/3213 ,  H01L23/00

CPC分类号： H01L23/5383 ,  H01L21/3213 ,  H01L21/566 ,  H01L21/76802 ,  H01L23/3128 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L24/09 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/73253 ,  H01L2924/15311

摘要： A semiconductor device includes a semiconductor die and a substrate having a first surface and a second surface. The semiconductor die is attached to the second surface. The substrate includes a layer of insulative material and an embedded conductive circuit in the layer of insulative material. The embedded conductive circuit includes an etched layer of a conductive material. The etched layer of the conductive material is located on the first surface of the substrate. The etched layer of the conductive material is made of a first metallic material and the embedded conductive circuit is made of a second metallic material that is different than the first metallic material.

公开(公告)号：US20190189493A1

公开(公告)日：2019-06-20

申请号：US16322863

申请日：2017-08-01

申请人： TOKYO ELECTRON LIMITED

发明人： Shuhei OGAWA ,  Keigo TOYODA ,  Yoshihide KIHARA

IPC分类号： H01L21/683 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/67 ,  H01J37/32

CPC分类号： H01L21/6833 ,  H01J37/32715 ,  H01J2237/20214 ,  H01J2237/3341 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31116 ,  H01L21/3213 ,  H01L21/67069 ,  H01L21/768 ,  H05H1/46

摘要： A method according to an embodiment includes: (a) a first step of etching a workpiece held by a holding structure in a state in which a first direction and a second direction are maintained to form a first angle, by a plasma generated in a processing container; and (a) a second step of, after execution of the first step, etching the workpiece held by the holding structure in a state in which the first direction and the second direction are maintained to form a second angle, by the plasma generated in the processing container.

公开(公告)号：US20190157431A1

公开(公告)日：2019-05-23

申请号：US15749101

申请日：2017-12-20

申请人： Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.

发明人： Chunsheng Jiang

IPC分类号： H01L29/66 ,  H01L27/12 ,  H01L29/45 ,  H01L21/3213

CPC分类号： H01L29/66969 ,  H01L21/02628 ,  H01L21/3213 ,  H01L27/1262 ,  H01L27/1274 ,  H01L29/45

摘要： The invention provides a BCE TFT substrate and manufacturing method thereof. The method comprises forming a first IGZO thin film with polycrystalline IGZO particles in a predetermined area of active layer before sputtering IGZO, the polycrystalline IGZO particles in the first IGZO thin film used as seed crystal during sputtering to grow a C-axis crystallized IGZO in good crystalline state to form a second IGZO thin film. The first and second IGZO thin films form an active layer. Because the surface of the active layer is presented as C-axis crystallized IGZO, the active layer is not damaged by the copper etchant during etching source and drain so as to ensure stable performance of active layer and to avoid the development of special copper etching solution. As such, the BCE TFT substrate has stable electrical performance. The BCE TFT substrate manufactured by the above manufacturing method has stable electrical performance.

公开(公告)号：US20180323226A1

公开(公告)日：2018-11-08

申请号：US15922514

申请日：2018-03-15

申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION ,  SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION

发明人： DEKUI QI ,  Fucheng Chen

IPC分类号： H01L27/146 ,  H01L21/28 ,  H01L21/768 ,  H01L21/3213

CPC分类号： H01L27/1464 ,  H01L21/28123 ,  H01L21/3213 ,  H01L21/76834 ,  H01L21/76849 ,  H01L27/14603 ,  H01L27/14645

摘要： A semiconductor device includes a device substrate having a dielectric layer and a metal wire in the dielectric layer, a first opening on the metal wire and having a bottom at a depth the same as an upper surface of the metal wire, a first insulation layer including a first color filter material on sidewalls of the first opening, a second opening disposed at opposite ends of the semiconductor device and having a bottom at a depth the same as the depth of the bottom of the first opening, and a second insulation layer including a second color filter material on sidewalls of the second opening. The first opening is for leading out the metal wire to a pad. The second opening is disposed along scribe lines. The semiconductor device simplifies the process of drawing out and isolating the pads and satisfies technical requirements of a back seal ring.

公开(公告)号：US20180277386A1

公开(公告)日：2018-09-27

申请号：US15904157

申请日：2018-02-23

申请人： Tokyo Electron Limited

发明人： Sonam D. Sherpa ,  Alok Ranjan

IPC分类号： H01L21/311 ,  H01L21/033

CPC分类号： H01L21/3065 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3213 ,  H01L21/32137

摘要： A method of preparing a self-aligned block (SAB) structure is described. The method includes providing a substrate having raised features defined by a first material containing silicon nitride and a second material containing silicon oxide formed on side walls of the first material, and a third material containing an organic material covering some of the raised features and exposing some raised features according to a block pattern formed in the third material. The method further includes forming a first chemical mixture by plasma-excitation of a first process gas containing H and optionally a noble gas, and exposing the first material on the substrate to the first chemical mixture. Thereafter, the method includes forming a second chemical mixture by plasma-excitation of a second process gas containing N, F, O, and optionally a noble element, and exposing the first material on the substrate to the second plasma-excited process gas to selectively etch the first material relative to the second and third material.

公开(公告)号：US20180102424A1

公开(公告)日：2018-04-12

申请号：US15831112

申请日：2017-12-04

申请人： Texas Instruments Incorporated

发明人： Yufei XIONG ,  Yunlong LIU ,  Hong YANG ,  Ho LIN ,  Tian Ping LV ,  Sheng ZOU ,  Qiu Ling JIA

IPC分类号： H01L29/739 ,  H01L21/3213 ,  H01L21/283 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/7397 ,  H01L21/283 ,  H01L21/3213 ,  H01L21/743 ,  H01L23/485 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/405 ,  H01L29/41766 ,  H01L29/7396 ,  H01L29/7398 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7827

摘要： A method of forming an IC including a power semiconductor device includes providing a substrate having an epi layer thereon with at least one transistor formed therein covered by a pre-metal dielectric (PMD) layer. Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact. A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.

公开(公告)号：US20180040485A1

公开(公告)日：2018-02-08

申请号：US15552258

申请日：2016-02-19

申请人： OSRAM Opto Semiconductors GmbH

发明人： Andreas RUECKERL ,  Roland ZEISEL ,  Simeon KATZ

IPC分类号： H01L21/3213 ,  H01L33/00 ,  H01S5/22 ,  H01L31/0232 ,  H01L31/0236 ,  H01L31/0304 ,  H01L33/44 ,  H01L21/02

CPC分类号： H01L21/3213 ,  H01L21/02389 ,  H01L31/02327 ,  H01L31/02366 ,  H01L31/03044 ,  H01L33/0075 ,  H01L33/44 ,  H01L2933/0025 ,  H01S5/22

摘要： The invention relates to a method for structuring a nitride layer (2), comprising the following steps: A) providing a nitride layer (2) formed with silicon nitride of a first type, B) defining regions (40) of said nitride layer (2) to be transformed, and C) inserting the nitride layer (2) into a transformation chamber for the duration of a transformation period, said transformation period being selected such that—at least 80% of the nitride layer (2) regions (40) to be transformed are transformed into oxide regions (41) formed with silicon oxide, and—remaining nitride layer (2) regions (21) remain at least 80% untransformed.

公开(公告)号：US09831428B2

公开(公告)日：2017-11-28

申请号：US14972152

申请日：2015-12-17

申请人： Micron Technology, Inc.

发明人： Marcello Ravasio ,  Samuele Sciarrillo ,  Andrea Gotti

IPC分类号： H01L45/00 ,  H01L27/105 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/24 ,  H01L27/22

CPC分类号： H01L45/124 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/1052 ,  H01L27/222 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/144 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

摘要： Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode.

公开(公告)号：US09768267B2

公开(公告)日：2017-09-19

申请号：US14755317

申请日：2015-06-30

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/423 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/42356 ,  H01L21/02532 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28525 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/32115 ,  H01L21/3213 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7827

摘要： An SGT is produced by forming a first insulating film around a fin-shaped semiconductor layer, forming a pillar-shaped semiconductor layer in an upper portion of the fin-shaped layer, forming a second insulating film, a polysilicon gate electrode covering the second insulating film, and a polysilicon gate line, forming a diffusion layer in an upper portion of the fin-shaped layer and a lower portion of the pillar-shaped layer, forming a metal-semiconductor compound in an upper portion of the diffusion layer in the fin-shaped layer, depositing an interlayer insulating film, exposing and etching the polysilicon gate electrode and gate line, depositing a first metal, forming a metal gate electrode and a metal gate line, and forming a third metal sidewall on an upper side wall of the pillar-shaped layer. The third metal sidewall is connected to an upper surface of the pillar-shaped layer.

公开(公告)号：US09679904B2

公开(公告)日：2017-06-13

申请号：US14612613

申请日：2015-02-03

申请人： FUJITSU SEMICONDUCTOR LIMITED

发明人： Wensheng Wang

IPC分类号： H01L27/115 ,  H01L27/11507 ,  H01L49/02 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3213

CPC分类号： H01L27/11507 ,  H01L21/02197 ,  H01L21/02356 ,  H01L21/28568 ,  H01L21/3213 ,  H01L28/55 ,  H01L28/56 ,  H01L28/65 ,  H01L28/75

摘要： A method of manufacturing a semiconductor device includes: forming a conductive film over a semiconductor substrate; forming a first ferroelectric film over the conductive film; forming an amorphous second ferroelectric film over the first ferroelectric film; forming a transition metal oxide material film containing ruthenium over the second ferroelectric film; forming a first conductive metal oxide film over the transition metal oxide material film without exposing the transition metal oxide material film to the air; annealing and crystallizing the second ferroelectric film; and patterning the first conductive metal oxide film, the first ferroelectric film, the second ferroelectric film, and the conductive film to form a ferroelectric capacitor.