公开(公告)号：US09991350B2

公开(公告)日：2018-06-05

申请号：US15188110

申请日：2016-06-21

Applicant: Texas Instruments Incorporated

Inventor： Hong Yang ,  Seetharaman Sridhar ,  Yufei Xiong ,  Yunlong Liu ,  Zachary K. Lee ,  Peng Hu

IPC: H01L23/48 ,  H01L29/417 ,  H01L29/78 ,  H01L29/732 ,  H01L29/739 ,  H01L21/288 ,  H01L21/285 ,  H01L29/08 ,  H01L29/423 ,  H01L23/485 ,  H01L23/535 ,  H01L21/74 ,  H01L29/06 ,  H01L29/45 ,  H01L29/10

CPC classification number: H01L29/41766 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/743 ,  H01L23/485 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/41708 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/456 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835

Abstract: An semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material. A method for forming a semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material.

公开(公告)号：US09461131B1

公开(公告)日：2016-10-04

申请号：US14739230

申请日：2015-06-15

Applicant: Texas Instruments Incorporated

Inventor： Yufei Xiong ,  Yunlong Liu ,  Hong Yang ,  Jianxin Liu

IPC: H01L21/336 ,  H01L27/108 ,  H01L29/423 ,  H01L27/088 ,  H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/28

CPC classification number: H01L27/088 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/308 ,  H01L23/5283 ,  H01L27/0629 ,  H01L28/40 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/66181 ,  H01L29/7827 ,  H01L29/945

Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.

Abstract translation: 一种集成电路，其包括在衬底中的沟槽，其具有在沟槽的侧壁和底部上生长的高质量沟槽氧化物，其中形成在侧壁上的高质量沟槽氧化物的厚度与形成在底部上的厚度之比较小 超过1.2。 包括具有高质量氧化物的沟槽的集成电路通过首先在1050℃至1250℃的温度范围内在稀释氧中生长牺牲氧化物而形成，剥离牺牲氧化物，在稀释氧中生长高质量的氧化物 在1050℃至1250℃的温度下加入反式1,2-二氯乙烯，并在1050℃至1250℃的温度范围内在惰性环境中退火高品质氧化物。

公开(公告)号：US20180061828A1

公开(公告)日：2018-03-01

申请号：US15790212

申请日：2017-10-23

Applicant: Texas Instruments Incorporated

Inventor： Yufei Xiong ,  Yunlong Liu ,  Hong Yang ,  Jianxin Liu

IPC: H01L27/088 ,  H01L29/94 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L49/02 ,  H01L27/06 ,  H01L23/528 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/265

CPC classification number: H01L27/088 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/308 ,  H01L23/5283 ,  H01L27/0629 ,  H01L28/40 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/66181 ,  H01L29/7827 ,  H01L29/945

Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.

公开(公告)号：US10347626B2

公开(公告)日：2019-07-09

申请号：US15790212

申请日：2017-10-23

Applicant: Texas Instruments Incorporated

Inventor： Yufei Xiong ,  Yunlong Liu ,  Hong Yang ,  Jianxin Liu

IPC: H01L29/423 ,  H01L27/088 ,  H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/28 ,  H01L29/66 ,  H01L29/94 ,  H01L23/528 ,  H01L29/49 ,  H01L21/02 ,  H01L21/306 ,  H01L21/265

Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.

公开(公告)号：US09825030B2

公开(公告)日：2017-11-21

申请号：US15255311

申请日：2016-09-02

Applicant: Texas Instruments Incorporated

Inventor： Yufei Xiong ,  Yunlong Liu ,  Hong Yang ,  Jianxin Liu

IPC: H01L27/108 ,  H01L27/088 ,  H01L29/423 ,  H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/28 ,  H01L29/66 ,  H01L29/94 ,  H01L23/528 ,  H01L29/49 ,  H01L21/265

CPC classification number: H01L27/088 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/308 ,  H01L23/5283 ,  H01L27/0629 ,  H01L28/40 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/66181 ,  H01L29/7827 ,  H01L29/945

Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.

公开(公告)号：US20160315155A1

公开(公告)日：2016-10-27

申请号：US15188188

申请日：2016-06-21

Applicant: Texas Instruments Incorporated

Inventor： Hong Yang ,  Zachary K. Lee ,  Yufei Xiong ,  Yunlong Liu ,  Wei Tang

IPC: H01L29/40 ,  H01L29/78

CPC classification number: H01L29/407 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/7834

Abstract: A method of fabricating a FET includes forming a gate on the surface of a substrate. A trench contact extends between a first region located proximate the surface of the substrate and a second region located below the first region is formed in the surface. The surface of the substrate is coated with a conductive material, wherein the conductive material at least partially covers the gate and lines the trench contact to electrically connect the first region and the second region. A void remains in the trench contact. A dielectric material is applied to the conductive material, wherein the dielectric material at least partially fills the void in the trench contact. At least a portion of the conductive material is etched from the gate.

Abstract translation: 一种制造FET的方法包括在衬底的表面上形成栅极。 沟槽接触部在位于基板表面附近的第一区域和位于第一区域下方的第二区域之间形成。 衬底的表面涂覆有导电材料，其中导电材料至少部分地覆盖栅极并对沟槽接触线进行导线以电连接第一区域和第二区域。 在沟槽接触处留下空隙。 介电材料被施加到导电材料上，其中电介质材料至少部分地填充沟槽接触中的空隙。 导电材料的至少一部分从栅极被蚀刻。

公开(公告)号：US09406774B1

公开(公告)日：2016-08-02

申请号：US14692337

申请日：2015-04-21

Applicant: Texas Instruments Incorporated

Inventor： Hong Yang ,  Zachary K. Lee ,  Yufei Xiong ,  Yunlong Liu ,  Wei Tang

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/407 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/7834

Abstract: A method of fabricating a FET includes forming a gate on the surface of a substrate. A trench contact extends between a first region located proximate the surface of the substrate and a second region located below the first region is formed in the surface. The surface of the substrate is coated with a conductive material, wherein the conductive material at least partially covers the gate and lines the trench contact to electrically connect the first region and the second region. A void remains in the trench contact. A dielectric material is applied to the conductive material, wherein the dielectric material at least partially fills the void in the trench contact. At least a portion of the conductive material is etched from the gate.

Abstract translation: 一种制造FET的方法包括在衬底的表面上形成栅极。 沟槽接触部在位于基板表面附近的第一区域和位于第一区域下方的第二区域之间形成。 衬底的表面涂覆有导电材料，其中导电材料至少部分地覆盖栅极并对沟槽接触线进行导线以电连接第一区域和第二区域。 在沟槽接触处留下空隙。 介电材料被施加到导电材料上，其中电介质材料至少部分地填充沟槽接触中的空隙。 导电材料的至少一部分从栅极被蚀刻。

公开(公告)号：US11037816B2

公开(公告)日：2021-06-15

申请号：US15649774

申请日：2017-07-14

Applicant: Texas Instruments Incorporated

Inventor： Hong Yang ,  Michael F Chisholm ,  Yufei Xiong ,  Yunlong Liu

IPC: H01L21/762 ,  C23C16/30

Abstract: In described examples, a device includes a semiconductor substrate; a buried layer; and a trench with inner walls extending from the buried layer to a surface of the semiconductor substrate, the trench having sidewalls, a bottom wall, a barrier layer including a titanium (Ti) layer covering the sidewalls and the bottom wall, and a filler including more than one layer of conductor material formed on the barrier layer.

公开(公告)号：US10903345B2

公开(公告)日：2021-01-26

申请号：US15831112

申请日：2017-12-04

Applicant: Texas Instruments Incorporated

Inventor： Yufei Xiong ,  Yunlong Liu ,  Hong Yang ,  Ho Lin ,  Tianping Lv ,  Sheng Zou ,  Qiuling Jia

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/10 ,  H01L29/78 ,  H01L29/417 ,  H01L21/74 ,  H01L23/485 ,  H01L21/283 ,  H01L21/3213 ,  H01L29/40 ,  H01L29/06

Abstract: A method of forming an IC including a power semiconductor device includes providing a substrate having an epi layer thereon with at least one transistor formed therein covered by a pre-metal dielectric (PMD) layer. Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact. A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.

公开(公告)号：US09865718B1

公开(公告)日：2018-01-09

申请号：US15342896

申请日：2016-11-03

Applicant: Texas Instruments Incorporated

Inventor： Yufei Xiong ,  Yunlong Liu ,  Hong Yang ,  Ho Lin ,  Tian Ping Lv ,  Sheng Zou ,  Qiu Ling Jia

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/78 ,  H01L21/283 ,  H01L21/3213

CPC classification number: H01L29/7397 ,  H01L21/283 ,  H01L21/3213 ,  H01L29/0653 ,  H01L29/7827

Abstract: A method of forming an IC including a power semiconductor device includes providing a substrate having an epi layer thereon with at least one transistor formed therein covered by a pre-metal dielectric (PMD) layer. Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact. A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.