公开(公告)号：US20230396251A1

公开(公告)日：2023-12-07

申请号：US17975880

申请日：2022-10-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sneha Shetty ,  Rajesh Yadav

IPC: H03K19/0175

CPC classification number: H03K19/017509

Abstract: An I/O module configured to operate over a range of voltage supplies includes a transmit path circuit and a receive path circuit that are each configured to convert a data signal between a core voltage domain and one of a first voltage domain (e.g., a high voltage domain) and a second voltage domain (e.g., a low voltage domain) in response to a mode select signal.

公开(公告)号：US20220209754A1

公开(公告)日：2022-06-30

申请号：US17179707

申请日：2021-02-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Krishna Reddy Mudimela Venkata ,  Jakeerali Shaik ,  Sneha Shetty ,  Swathy Lal

IPC: H03K3/3565 ,  H03K5/06 ,  H03K19/00

Abstract: An assembly includes a signal input, a signal output, a pull-up stack coupled to the signal input and to the signal output, a pull-down stack coupled to the signal input and to the signal output, and a hysteresis assembly coupled to the pull-up stack and to the pull-down stack. The pull-up stack comprises a pair of metal oxide semiconductor field-effect transistors (transistors) coupled in series, each transistor of the pair of transistors comprising a gate coupled to the signal input. The pull-down stack comprises a plurality of transistors coupled in series, the plurality of transistors comprising: a first transistor comprising a gate coupled to the signal input, a second transistor comprising a gate coupled to the signal input, and a third transistor. The hysteresis assembly comprises a pair of transistors, each transistor of the pair of transistors of the hysteresis assembly having a gate coupled to the signal output.

公开(公告)号：US11303277B2

公开(公告)日：2022-04-12

申请号：US17074711

申请日：2020-10-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Krishna Reddy Mudimela Venkata ,  Sneha Shetty ,  Sankar Debnath

IPC: H03K19/0185 ,  H03K3/037

Abstract: A circuit includes first through fifth transistors. The first transistor has a first control input and first and second current terminals. The second transistor has a second control input and third and fourth current terminals. The third transistor has a third control input and fifth and sixth current terminals. The third control input is coupled to the third current terminal, and the fifth current terminal is coupled to a supply voltage node. The fourth transistor has a fourth control input and seventh and eighth current terminals. The fourth control input is coupled to the first current terminal, and the seventh current terminal coupled to the supply voltage node. The fifth transistor has a fifth control input and ninth and tenth current terminals. The fifth control input is coupled to the first control input, and the tenth current terminal coupled to the second current terminal.