公开(公告)号：US20210184659A1

公开(公告)日：2021-06-17

申请号：US16713343

申请日：2019-12-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Badarish Mohan SUBBANNAVAR ,  Arnab KHAWAS ,  Suvam NANDI

IPC: H03K3/037 ,  H03K3/012

Abstract: A flip-flop having first and second shared transistors. The flip-flop including a tri-state inverter and a master latch configured to receive an output of the tri-state inverter. The flip-flop also having a slave latch coupled to the master latch, the slave latch including a slave tri-state inverter. The flip-flop further having an output inverter coupled to receive one of an output of the slave latch and an output of the master latch and configured to generate a flip-flop output. The first shared transistor configured to receive a clock signal and having a drain terminal coupled a first transistor in the tri-state inverter and a second transistor in the slave tri-state inverter. The second shared transistor configured to receive an inverted clock signal and having a drain terminal coupled a third transistor in the tri-state inverter and a fourth transistor in the slave tri-state inverter.

公开(公告)号：US20170324423A1

公开(公告)日：2017-11-09

申请号：US15392491

申请日：2016-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal TANGUDU ,  Suvam NANDI ,  Jaiganesh BALAKRISHNAN

IPC: H03M7/30 ,  H03H17/06

CPC classification number: H03M7/6047 ,  H03D7/165 ,  H03D2200/0056 ,  H03H17/0664 ,  H03M7/3059

Abstract: A digital down converter includes a low resolution mixer, a decimation filter, and a high resolution mixer. The low resolution mixer is configured to receive a digitized radio frequency signal, and apply a first down conversion to the radio frequency signal to produce an intermediate frequency signal. The decimation filter is coupled to the low resolution mixer. The decimation filter is configured to receive the intermediate frequency signal, and reduce a sampling rate of the intermediate frequency signal to produce a decimated intermediate frequency signal. The high resolution mixer is coupled to the decimation filter. The high resolution mixer is configured to receive the decimated intermediate frequency signal, and apply a second down conversion to the decimated intermediate frequency signal to produce a down converted signal.

公开(公告)号：US20210265985A1

公开(公告)日：2021-08-26

申请号：US17319505

申请日：2021-05-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Badarish Mohan SUBBANNAVAR ,  Arnab KHAWAS ,  Suvam NANDI

IPC: H03K3/037 ,  H03K3/012

Abstract: A flip-flop having first and second shared transistors. The flip-flop including a tri-state inverter and a master latch configured to receive an output of the tri-state inverter. The flip-flop also having a slave latch coupled to the master latch, the slave latch including a slave tri-state inverter. The flip-flop further having an output inverter coupled to receive one of an output of the slave latch and an output of the master latch and configured to generate a flip-flop output. The first shared transistor configured to receive a clock signal and having a drain terminal coupled a first transistor in the tri-state inverter and a second transistor in the slave tri-state inverter. The second shared transistor configured to receive an inverted clock signal and having a drain terminal coupled a third transistor in the tri-state inverter and a fourth transistor in the slave tri-state inverter.

公开(公告)号：US20180241413A1

公开(公告)日：2018-08-23

申请号：US15960591

申请日：2018-04-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal TANGUDU ,  Suvam NANDI ,  Jaiganesh BALAKRISHNAN

IPC: H03M7/30 ,  H03D7/16 ,  H03H17/06

Abstract: A digital down converter includes a low resolution mixer, a decimation filter, and a high resolution mixer. The low resolution mixer is configured to receive a digitized radio frequency signal, and apply a first down conversion to the radio frequency signal to produce an intermediate frequency signal. The decimation filter is coupled to the low resolution mixer. The decimation filter is configured to receive the intermediate frequency signal, and reduce a sampling rate of the intermediate frequency signal to produce a decimated intermediate frequency signal. The high resolution mixer is coupled to the decimation filter. The high resolution mixer is configured to receive the decimated intermediate frequency signal, and apply a second down conversion to the decimated intermediate frequency signal to produce a down converted signal.

公开(公告)号：US20170322773A1

公开(公告)日：2017-11-09

申请号：US15587096

申请日：2017-05-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal TANGUDU ,  Suvam NANDI ,  Pooja SUNDAR ,  Jaiganesh BALAKRISHNAN

IPC: G06F7/523 ,  H03D7/16 ,  G06F7/50

CPC classification number: G06F7/523 ,  G06F7/50 ,  H03D7/161

Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.

公开(公告)号：US20170194943A1

公开(公告)日：2017-07-06

申请号：US15391465

申请日：2016-12-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Suvam NANDI ,  Badarish Mohan SUBBANNAVAR

IPC: H03K3/012 ,  H03K19/00 ,  H03K3/3562

CPC classification number: H03K3/012 ,  H03K3/35625 ,  H03K19/0002 ,  H03K19/09429

Abstract: At least some embodiments are directed to a flip-flop that comprises a tri-state inverter and a master latch coupled to the tri-state inverter and comprising a first transistor, a first inverter, and a first logic gate. The master latch receives a clock signal. The flop also comprises a slave latch coupled to the master latch and comprising a second transistor and a second inverter. The slave latch receives the clock signal. The flop further comprises an enablement logic coupled to the master latch and comprising multiple, additional logic gates. The tri-state inverter, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static.