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公开(公告)号：US11509294B2
公开(公告)日：2022-11-22
申请号：US17319505
申请日：2021-05-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Badarish Mohan Subbannavar , Arnab Khawas , Suvam Nandi
Abstract: A flip-flop having first and second shared transistors. The flip-flop including a tri-state inverter and a master latch configured to receive an output of the tri-state inverter. The flip-flop also having a slave latch coupled to the master latch, the slave latch including a slave tri-state inverter. The flip-flop further having an output inverter coupled to receive one of an output of the slave latch and an output of the master latch and configured to generate a flip-flop output. The first shared transistor configured to receive a clock signal and having a drain terminal coupled a first transistor in the tri-state inverter and a second transistor in the slave tri-state inverter. The second shared transistor configured to receive an inverted clock signal and having a drain terminal coupled a third transistor in the tri-state inverter and a fourth transistor in the slave tri-state inverter.
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公开(公告)号：US09985650B2
公开(公告)日：2018-05-29
申请号：US15392491
申请日：2016-12-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jawaharlal Tangudu , Suvam Nandi , Jaiganesh Balakrishnan
CPC classification number: H03M7/6047 , H03D7/165 , H03D2200/0056 , H03H17/0664 , H03M7/3059
Abstract: A digital down converter includes a low resolution mixer, a decimation filter, and a high resolution mixer. The low resolution mixer is configured to receive a digitized radio frequency signal, and apply a first down conversion to the radio frequency signal to produce an intermediate frequency signal. The decimation filter is coupled to the low resolution mixer. The decimation filter is configured to receive the intermediate frequency signal, and reduce a sampling rate of the intermediate frequency signal to produce a decimated intermediate frequency signal. The high resolution mixer is coupled to the decimation filter. The high resolution mixer is configured to receive the decimated intermediate frequency signal, and apply a second down conversion to the decimated intermediate frequency signal to produce a down converted signal.
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公开(公告)号：US09350327B2
公开(公告)日：2016-05-24
申请号：US14498412
申请日：2014-09-26
Applicant: Texas Instruments Incorporated
Inventor： Suvam Nandi , Badarish Mohan Subbannavar
CPC classification number: H03K3/012 , H03K3/0372
Abstract: The disclosure provides a flip-flop that utilizes low power as a result of reduced transistor count. The flip-flop includes a tri-state inverter that receives a flip-flop input and a clock input. A master latch is coupled to an output of the tri-state inverter and provides a control signal to the tri-state inverter. The control signal activates the tri-state inverter. A slave latch receives an output of the master latch and the control signal. An output inverter is coupled to an output of the slave latch and generates a flip-flop output.
Abstract translation: 本公开提供了一种触发器，其由于晶体管数量减少而利用低功率。 触发器包括接收触发器输入和时钟输入的三态反相器。 主锁存器耦合到三态反相器的输出，并向三态反相器提供控制信号。 控制信号激活三态变频器。 从锁存器接收主锁存器和控制信号的输出。 输出反相器耦合到从锁存器的输出并产生触发器输出。
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公开(公告)号：US20200301666A1
公开(公告)日：2020-09-24
申请号：US16852710
申请日：2020-04-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jawaharlal Tangudu , Suvam Nandi , Pooja Sundar , Jaiganesh Balakrishnan
Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.
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公开(公告)号：US10396829B2
公开(公告)日：2019-08-27
申请号：US16110478
申请日：2018-08-23
Applicant: Texas Instruments Incorporated
Inventor： Jaiganesh Balakrishnan , Suvam Nandi , Sundarrajan Rangachari
Abstract: A digital filter for interpolation or decimation and a device incorporating the digital filter is disclosed. The digital filter includes a filter block, a first transformation circuit coupled to the filter block and an input stream coupled to provide input values to a component selected from the filter block and the first transformation circuit. The filter block includes a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric. The first transformation circuit is coupled to perform a first transformation; the filter block and the first transformation circuit together provide suppression of undesired spectral images in final outputs of the digital filter.
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Patent Agency Ranking
公开(公告)号：US20180331675A1
公开(公告)日：2018-11-15
申请号：US16042194
申请日：2018-07-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Suvam Nandi , Badarish Mohan Subbannavar
IPC: H03K3/012 , H03K19/094 , H03K3/3562 , H03K19/00
CPC classification number: H03K3/3562 , H03K3/012 , H03K3/356147 , H03K3/356156 , H03K3/356191 , H03K3/35625 , H03K19/0002 , H03K19/09429
Abstract: At least some embodiments are directed to a flip-flop that comprises a tri-state inverter and a master latch coupled to the tri-state inverter and comprising a first transistor, a first inverter, and a first logic gate. The master latch receives a clock signal. The flop also comprises a slave latch coupled to the master latch and comprising a second transistor and a second inverter. The slave latch receives the clock signal. The flop further comprises an enablement logic coupled to the master latch and comprising multiple, additional logic gates. The tri-state inverter, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static.
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公开(公告)号：US10056882B2
公开(公告)日：2018-08-21
申请号：US15391465
申请日：2016-12-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Suvam Nandi , Badarish Mohan Subbannavar
IPC: H03K3/012 , H03K3/3562 , H03K19/00 , H03K19/094
CPC classification number: H03K3/3562 , H03K3/012 , H03K3/356147 , H03K3/356156 , H03K3/356191 , H03K3/35625 , H03K19/0002 , H03K19/09429
Abstract: At least some embodiments are directed to a flip-flop that comprises a tri-state inverter and a master latch coupled to the tri-state inverter and comprising a first transistor, a first inverter, and a first logic gate. The master latch receives a clock signal. The flop also comprises a slave latch coupled to the master latch and comprising a second transistor and a second inverter. The slave latch receives the clock signal. The flop further comprises an enablement logic coupled to the master latch and comprising multiple, additional logic gates. The tri-state inverter, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static.
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公开(公告)号：US20190319612A1
公开(公告)日：2019-10-17
申请号：US16452597
申请日：2019-06-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Suvam Nandi , Badarish Mohan Subbannavar
IPC: H03K3/3562 , H03K19/094 , H03K3/356 , H03K3/012 , H03K19/00
Abstract: At least some embodiments are directed to a flip-flop that comprises a tri-state inverter and a master latch coupled to the tri-state inverter and comprising a first transistor, a first inverter, and a first logic gate. The master latch receives a clock signal. The flop also comprises a slave latch coupled to the master latch and comprising a second transistor and a second inverter. The slave latch receives the clock signal. The flop further comprises an enablement logic coupled to the master latch and comprising multiple, additional logic gates. The tri-state inverter, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static.
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公开(公告)号：US10382020B2
公开(公告)日：2019-08-13
申请号：US16042194
申请日：2018-07-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Suvam Nandi , Badarish Mohan Subbannavar
IPC: H03K3/3562 , H03K3/012 , H03K19/00 , H03K19/094 , H03K3/356
Abstract: At least some embodiments are directed to a flip-flop that comprises a tri-state inverter and a master latch coupled to the tri-state inverter and comprising a first transistor, a first inverter, and a first logic gate. The master latch receives a clock signal. The flop also comprises a slave latch coupled to the master latch and comprising a second transistor and a second inverter. The slave latch receives the clock signal. The flop further comprises an enablement logic coupled to the master latch and comprising multiple, additional logic gates. The tri-state inverter, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static.
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公开(公告)号：US10372415B2
公开(公告)日：2019-08-06
申请号：US15587096
申请日：2017-05-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jawaharlal Tangudu , Suvam Nandi , Pooja Sundar , Jaiganesh Balakrishnan
Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.
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