公开(公告)号：US20180188313A1

公开(公告)日：2018-07-05

申请号：US15395907

申请日：2016-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alex PAIKIN ,  Colin JOHNSON ,  Tathagata CHATTERJEE ,  Sameer PENDHARKAR

IPC: G01R31/26 ,  G01R31/28

CPC classification number: G01R31/2628 ,  G01R31/2849

Abstract: In at least some embodiments, a system comprises a socket gate terminal configured to receive a first voltage to activate and inactivate a device under test (DUT) coupled to the socket gate terminal. The system also comprises a socket source terminal configured to provide a reference voltage to the DUT. The system further comprises a socket drain terminal configured to provide a second voltage to the DUT to stress the DUT when the DUT is inactive. The socket drain terminal is further configured to receive a third voltage to cause a current to flow through a pathway in the DUT between the socket drain terminal and the socket source terminal when the DUT is active. The socket drain terminal is further configured to provide a fourth voltage indicative of a resistance of the pathway in the DUT when the DUT is active and is heated to a temperature above an ambient temperature associated with the system.

公开(公告)号：US20190204375A1

公开(公告)日：2019-07-04

申请号：US15859244

申请日：2017-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yuguo WANG ,  Steven LOVELESS ,  Tathagata CHATTERJEE ,  Jerry DOORENBOS

IPC: G01R31/26

CPC classification number: G01R31/2626

Abstract: A system comprises a noise generator circuit and a noise envelope detector circuit. The noise generator circuit comprises a first amplifier including a single transistor pair that is operable to generate 1/f noise, an output amplifier coupled to the first amplifier and configured to generate a 1/f noise signal as a function of the 1/f noise. The noise envelope detector circuit comprises a low pass filter operable to pass low frequency signals of the 1/f noise signal as a filtered 1/f noise signal, and a second amplifier or a comparator coupled to the low pass filter and operable to output a direct current (DC) voltage signal according to an envelope of the filtered 1/f noise signal, where the DC voltage signal is a function of an envelope of the filtered 1/f noise signal.

公开(公告)号：US20190181874A1

公开(公告)日：2019-06-13

申请号：US16266470

申请日：2019-02-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven John LOVELESS ,  Yuguo WANG ,  Tathagata CHATTERJEE ,  Robert Stanley GRONDALSKI

IPC: H03M1/10 ,  H03K21/08 ,  G01R27/26 ,  H03K5/24

Abstract: An analog-to-digital converter (ADC) comprising successive approximation circuitry, a capacitive analog-to-digital converter (CDAC), and capacitor mismatch measurement circuitry. The successive approximation circuitry is configured to control conversion of an analog signal to a digital value. The CDAC is coupled to the successive approximation circuitry. The CDAC includes a plurality of capacitors. The capacitor mismatch measurement circuitry is coupled to the CDAC. The capacitor mismatch measurement circuitry includes a first oscillator circuit, a second oscillator circuit, and counter circuitry. The first oscillator circuit is configured to oscillate at a frequency determined by a capacitance of one of the capacitors. The second oscillator circuit is configured to generate a predetermined time interval. The counter circuitry is configured to count a number of cycles of oscillation of the first oscillator in the predetermined time interval.

公开(公告)号：US20190011493A1

公开(公告)日：2019-01-10

申请号：US16130035

申请日：2018-09-13

Applicant: Texas Instruments Incorporated

Inventor： Alex PAIKIN ,  Colin JOHNSON ,  Tathagata CHATTERJEE ,  Sameer PENDHARKAR

IPC: G01R31/26 ,  G01R31/28

CPC classification number: G01R31/2628 ,  G01R31/2642 ,  G01R31/2849

Abstract: In at least some embodiments, a system comprises a socket gate terminal configured to receive a first voltage to activate and inactivate a device under test (DUT) coupled to the socket gate terminal. The system also comprises a socket source terminal configured to provide a reference voltage to the DUT. The system further comprises a socket drain terminal configured to provide a second voltage to the DUT to stress the DUT when the DUT is inactive. The socket drain terminal is further configured to receive a third voltage to cause a current to flow through a pathway in the DUT between the socket drain terminal and the socket source terminal when the DUT is active. The socket drain terminal is further configured to provide a fourth voltage indicative of a resistance of the pathway in the DUT when the DUT is active and is heated to a temperature above an ambient temperature associated with the system.