公开(公告)号：US10348298B2

公开(公告)日：2019-07-09

申请号：US15875573

申请日：2018-01-19

Applicant: Texas Instruments Incorporated

Inventor： Vikas Suma Vinay ,  Tatsuyuki Nihei ,  Christopher Lewis Kraft

IPC: G06F13/42 ,  H03K19/00 ,  H03K19/0185 ,  G01R31/30

Abstract: This disclosure generally relates to repeaters, and, in particular, repeaters for open-drain systems. In one embodiment, an apparatus comprises a first port, a second port, a current detector, a transistor, and a control logic circuit. A current detector input of the current detector is coupled to the first port. A transistor channel electrode of the transistor is coupled to the second port. A control logic circuit input of the control logic circuit is coupled to the current detector output, and a control logic circuit output of the control logic circuit is coupled to a transistor control electrode of the transistor.

公开(公告)号：US09082473B2

公开(公告)日：2015-07-14

申请号：US13785583

申请日：2013-03-05

Applicant: Texas Instruments Incorporated

Inventor： Abidur Rahman ,  Tatsuyuki Nihei ,  Tatsuro Sato ,  Uchino Osamu

IPC: G11C11/22 ,  G11C5/14

CPC classification number: G11C5/148 ,  G11C11/2297

Abstract: Corruption of data in a FRAM (2) is avoided by applying a regulated voltage (VLDO) to a conductive pin (5-1). A switch (SW1) is coupled between the conductive pin and a power terminal of the FRAM so a FRAM supply voltage (VFRAM) is equal to the regulated voltage when the switch is closed. The conductive pin is coupled to a power terminal of a digital circuit (3) so a digital circuit supply voltage (VCORE) is equal to the regulated voltage. A power interruption is detected to produce an interruption signal (nBORdet) that opens the switch and also prevents starting of new read and write operations in the FRAM. A sufficient FRAM supply voltage is maintained by an internal capacitor (CINT) while ongoing read and write operations in the FRAM are completed during a predetermined interval. The conductive pin may be coupled to the switch by bonding wire inductance (LWIRE) between the switch and the conductive pin to inhibit flow of transient currents between them.

Abstract translation: 通过将调节电压（VLDO）施加到导电针（5-1）来避免FRAM（2）中的数据损坏。 开关（SW1）耦合在导电引脚和FRAM的电源端子之间，因此当开关闭合时，FRAM电源电压（VFRAM）等于调节电压。 导电引脚耦合到数字电路（3）的电源端子，因此数字电路电源电压（VCORE）等于调节电压。 检测到电源中断以产生打开该开关的中断信号（nBORdet），并且还防止在FRAM中启动新的读取和写入操作。 在FRAM中进行的读写操作在预定间隔内完成时，由内部电容器（CINT）维持足够的FRAM电源电压。 可以通过在开关和导电引脚之间接合线电感（LWIRE）来将导电引脚耦合到开关，以抑制它们之间的瞬态电流的流动。

公开(公告)号：US20200266819A1

公开(公告)日：2020-08-20

申请号：US16869619

申请日：2020-05-08

Applicant: Texas Instruments Incorporated

Inventor： Vikas Suma Vinay ,  Tatsuyuki Nihei ,  Christopher Lewis Kraft

IPC: H03K19/00 ,  H03K19/0185 ,  G01R31/30

Abstract: This disclosure generally relates to repeaters, and, in particular, repeaters for open-drain systems. In one embodiment, an apparatus comprises a first port, a second port, a current detector, a transistor, and a control logic circuit. A current detector input of the current detector is coupled to the first port. A transistor channel electrode of the transistor is coupled to the second port. A control logic circuit input of the control logic circuit is coupled to the current detector output, and a control logic circuit output of the control logic circuit is coupled to a transistor control electrode of the transistor.

公开(公告)号：US10686441B2

公开(公告)日：2020-06-16

申请号：US16421000

申请日：2019-05-23

Applicant: Texas Instruments Incorporated

Inventor： Vikas Suma Vinay ,  Tatsuyuki Nihei ,  Christopher Lewis Kraft

IPC: H03K19/00 ,  H03K19/0185 ,  G01R31/30 ,  G06F13/42

Abstract: This disclosure generally relates to repeaters, and, in particular, repeaters for open-drain systems. In one embodiment, an apparatus comprises a first port, a second port, a current detector, a transistor, and a control logic circuit. A current detector input of the current detector is coupled to the first port. A transistor channel electrode of the transistor is coupled to the second port. A control logic circuit input of the control logic circuit is coupled to the current detector output, and a control logic circuit output of the control logic circuit is coupled to a transistor control electrode of the transistor.

公开(公告)号：US11133802B2

公开(公告)日：2021-09-28

申请号：US16869619

申请日：2020-05-08

Applicant: Texas Instruments Incorporated

Inventor： Vikas Suma Vinay ,  Tatsuyuki Nihei ,  Christopher Lewis Kraft

IPC: H03K19/00 ,  H03K19/0185 ,  G01R31/30 ,  G06F13/42

Abstract: This disclosure generally relates to repeaters, and, in particular, repeaters for open-drain systems. In one embodiment, an apparatus comprises a first port, a second port, a current detector, a transistor, and a control logic circuit. A current detector input of the current detector is coupled to the first port. A transistor channel electrode of the transistor is coupled to the second port. A control logic circuit input of the control logic circuit is coupled to the current detector output, and a control logic circuit output of the control logic circuit is coupled to a transistor control electrode of the transistor.

公开(公告)号：US20190280692A1

公开(公告)日：2019-09-12

申请号：US16421000

申请日：2019-05-23

Applicant: Texas Instruments Incorporated

Inventor： Vikas Suma Vinay ,  Tatsuyuki Nihei ,  Christopher Lewis Kraft

IPC: H03K19/00 ,  H03K19/0185 ,  G01R31/30

Abstract: This disclosure generally relates to repeaters, and, in particular, repeaters for open-drain systems. In one embodiment, an apparatus comprises a first port, a second port, a current detector, a transistor, and a control logic circuit. A current detector input of the current detector is coupled to the first port. A transistor channel electrode of the transistor is coupled to the second port. A control logic circuit input of the control logic circuit is coupled to the current detector output, and a control logic circuit output of the control logic circuit is coupled to a transistor control electrode of the transistor.

公开(公告)号：US20180323785A1

公开(公告)日：2018-11-08

申请号：US15875573

申请日：2018-01-19

Applicant: Texas Instruments Incorporated

Inventor： Vikas Suma Vinay ,  Tatsuyuki Nihei ,  Christopher Lewis Kraft

IPC: H03K19/00 ,  H03K19/0185 ,  G01R31/30 ,  G06F13/42

CPC classification number: H03K19/0008 ,  G01R31/3004 ,  G06F13/4282 ,  G06F2213/0016 ,  H03K19/0185

Abstract: This disclosure generally relates to repeaters, and, in particular, repeaters for open-drain systems. In one embodiment, an apparatus comprises a first port, a second port, a current detector, a transistor, and a control logic circuit. A current detector input of the current detector is coupled to the first port. A transistor channel electrode of the transistor is coupled to the second port. A control logic circuit input of the control logic circuit is coupled to the current detector output, and a control logic circuit output of the control logic circuit is coupled to a transistor control electrode of the transistor.

公开(公告)号：US20140254235A1

公开(公告)日：2014-09-11

申请号：US13785583

申请日：2013-03-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abidur Rahman ,  Tatsuyuki Nihei ,  Tatsuro Sato ,  Uchino Osamu

IPC: G11C5/14

CPC classification number: G11C5/148 ,  G11C11/2297

Abstract: Corruption of data in a FRAM (2) is avoided by applying a regulated voltage (VLDO) to a conductive pin (5-1). A switch (SW1) is coupled between the conductive pin and a power terminal of the FRAM so a FRAM supply voltage (VFRAM) is equal to the regulated voltage when the switch is closed. The conductive pin is coupled to a power terminal of a digital circuit (3) so a digital circuit supply voltage (VCORE) is equal to the regulated voltage. A power interruption is detected to produce an interruption signal (nBORdet) that opens the switch and also prevents starting of new read and write operations in the FRAM. A sufficient FRAM supply voltage is maintained by an internal capacitor (CINT) while ongoing read and write operations in the FRAM are completed during a predetermined interval. The conductive pin may be coupled to the switch by bonding wire inductance (LWIRE) between the switch and the conductive pin to inhibit flow of transient currents between them.

Abstract translation: 通过将调节电压（VLDO）施加到导电针（5-1）来避免FRAM（2）中的数据损坏。 开关（SW1）耦合在导电引脚和FRAM的电源端子之间，因此当开关闭合时，FRAM电源电压（VFRAM）等于调节电压。 导电引脚耦合到数字电路（3）的电源端子，因此数字电路电源电压（VCORE）等于调节电压。 检测到电源中断以产生打开该开关的中断信号（nBORdet），并且还防止在FRAM中启动新的读取和写入操作。 在FRAM中进行的读写操作在预定间隔内完成时，由内部电容器（CINT）维持足够的FRAM电源电压。 可以通过在开关和导电引脚之间接合线电感（LWIRE）来将导电引脚耦合到开关，以抑制它们之间的瞬态电流的流动。