公开(公告)号：US20220165318A1

公开(公告)日：2022-05-26

申请号：US16953602

申请日：2020-11-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mayank GARG ,  Srijan RASTOGI ,  Vivekkumar Ramanlal VADODARIYA ,  Nitesh KEKRE

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/20

Abstract: A serial bus equalization trim circuit includes a first data input terminal, a second data input terminal, a delay circuit, and a flip-flop. The delay circuit includes a data input, a trim input, and an output. The data input is coupled the first data input terminal. The flip-flop includes a data input, a clock input, and an output. The data input is coupled to the output of the delay circuit. The clock input is coupled to the second data input terminal. The output is coupled to the trim input of the delay circuit.

公开(公告)号：US20220391345A1

公开(公告)日：2022-12-08

申请号：US17341089

申请日：2021-06-07

Applicant: Texas Instruments Incorporated

Inventor： Anant Shankar KAMATH ,  Rakesh HARIHARAN ,  Vivekkumar Ramanlal VADODARIYA ,  Soumi PAUL ,  Mayank GARG

IPC: G06F13/42 ,  G06F13/38 ,  G06F1/3215

Abstract: A bus repeater includes first and second bus ports, a first termination resistor network coupled to the first bus port, a second termination resistor network coupled to the second bus port, and a power state change detection circuit coupled to the second bus port. The power state change detection circuit is configured to detect a power state change initiated by a device coupled to the first bus port. The detection of the power state change includes a determination that a voltage on the second bus port exceeds a threshold. Responsive to detection of the power state change, the power state change detection circuit is configured cause a change in a configuration of at least one of the first or second termination resistor networks.