公开(公告)号：US20190296695A1

公开(公告)日：2019-09-26

申请号：US15934467

申请日：2018-03-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shyamsunder BALASUBRAMANIAN ,  Wenxiao TAN ,  Mayank GARG ,  Toru TANAKA

IPC: H03F1/30 ,  H03F3/04

Abstract: An offset drift compensation circuit for correcting offset drift that changes with temperature. In one example, offset drift compensation circuit includes a low temperature offset compensation circuit and a high temperature offset circuit. The low temperature offset compensation circuit is configured to compensate for drift in offset at a first rate below a selected temperature. The high temperature offset compensation circuit is configured to compensate for drift in offset at a second rate above the selected temperature. The first rate is different from the second rate.

公开(公告)号：US20200044635A1

公开(公告)日：2020-02-06

申请号：US16428345

申请日：2019-05-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shuing JU ,  Wenxiao TAN ,  Arun RAO

IPC: H03K4/48

Abstract: Aspects provide for a circuit including a voltage supply, a driver, and a feedback bias circuit. The driver includes a first p-type field effect transistor (FET) and a first n-type FET. The voltage supply has an input and an output. The driver has a first input coupled to the voltage supply output, a second input coupled to a first node, and an output coupled to a second node. The first p-type FET has a gate coupled to the output of the driver, a source coupled to the voltage supply output, and a drain coupled to the second node. The first n-type FET has a gate coupled to the output of the second driver, a drain coupled to the second node, and a source coupled to a ground node. The feedback bias circuit has an input coupled to the second node and an output coupled to the voltage supply input.

公开(公告)号：US20170288622A1

公开(公告)日：2017-10-05

申请号：US15142134

申请日：2016-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Wenxiao TAN ,  Mayank GARG ,  Noble NARKU-TETTEH

IPC: H03F3/45 ,  H02P31/00 ,  G11C7/06 ,  H03F1/56

CPC classification number: H03F3/45677 ,  G11C7/06 ,  G11C29/028 ,  G11C29/50008 ,  G11C2029/0407 ,  H02P31/00 ,  H03F1/56 ,  H03F3/45179 ,  H03F2200/481 ,  H03F2203/45306

Abstract: An electrical device (e.g., an integrated circuit) includes an amplifier, a configurable common mode gain trim circuit, and a memory. The configurable common mode gain trim circuit is coupled to the amplifier. The memory is configured to include trim data that is usable during an initialization process for the electrical device to configure the impedance matching circuit.