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公开(公告)号:US10090871B2
公开(公告)日:2018-10-02
申请号:US14916954
申请日:2014-10-14
Applicant: THALES
Inventor: Patrick Garrec , Jean-Philippe Plaze , Benoit Mallet Guy
Abstract: A method managing the energy consumption of at least one electronic component in a radar reception chain, comprises a preliminary step of formulating a table containing values representative of the power level of received signals, each value being contained in a bin addressed by a triplet formed of a quantity corresponding to a measurement of the power level of a signal received from a target, of a quantity corresponding to the distance of the target and of a quantity corresponding to the azimuth of the target, the method performing for each received signal, arising from a radar recurrence of order n, the following steps: a step of reading a measurement of the power level of the received signal; a step of addressing the table as a function of the measurement, distance and azimuth of the target, a first power level value then being addressed; a step of extrapolating the power level of the next received signal arising from the following radar recurrence of order n+1, dependent on the first value and on a given number of values of the table addressed by sliding of addresses from the address of the first value according to the power level measurement addresses, the given number being dependent on the speed of the carrier of the reception chain, the step being applied for the received signal of order n+1, the setpoint value of the consumption being dependent at least on the extrapolation of the power level received and the position of the target.
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公开(公告)号:US09755586B2
公开(公告)日:2017-09-05
申请号:US15035561
申请日:2014-11-18
Applicant: Thales
Inventor: Jean-Philippe Plaze , Vincent Petit , Benoît Mallet-Guy
CPC classification number: H03F1/52 , H03F3/19 , H03F2200/211 , H03F2200/294 , H03F2200/444 , H03F2200/451 , H03G7/00 , H03G11/00 , H03G11/002 , H03G11/02 , H03G11/06
Abstract: This radiofrequency power limiter includes at least one transistor, a drain of the transistor being directly connected to a mesh connecting an input to an output of the limiter, a source of the transistor being connected to a common reference potential, and a gate of the transistor being connected to a common control potential. The transistor is not biased between its drain and its source during operation of the limiter.
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