公开(公告)号：US10892221B2

公开(公告)日：2021-01-12

申请号：US15739721

申请日：2016-06-24

Applicant: Thales ,  Université de Bordeaux ,  Institut Polytechnique de Bordeaux ,  Centre National de la Recherche Scientifique

Inventor： Victor Dupuy ,  Benoît Mallet-Guy ,  Yves Mancuso ,  Eric Kerherve

IPC: H01L23/52 ,  H01F17/00 ,  H01L23/522 ,  H01F27/28 ,  H01P5/18 ,  H01P5/12 ,  H01L23/66

Abstract: This transformer includes primary and secondary tracks (10, 20) that are coupled to one another by mutual inductance, the primary and secondary tracks being superimposed on top of each other in two parallel planes while being arranged to follow the same contour (C), the plane of the primary track corresponding to the main conductive layer of the circuit, said layer being deposited on a substrate (30), and the secondary track being supported, plumb with the primary track, by supporting means including walls (41-46; 51-56), each wall bearing directly on the substrate and against a lower surface (24) of the secondary track (20), and having a length (L) larger than a width (I), and having a height allowing a predetermined interval to be created between an upper surface (14) of the primary track (10) and the lower surface (24) of the secondary track (20).

公开(公告)号：US20180197816A1

公开(公告)日：2018-07-12

申请号：US15739721

申请日：2017-06-24

Applicant: Thales ,  Université de Bordeaux ,  Institut Polytechnique de Bordeaux ,  Centre National de la Recherche Scientifique

Inventor： Victor Dupuy ,  Benoît Mallet-Guy ,  Yves Mancuso ,  Eric Kerherve

IPC: H01L23/522 ,  H01L23/66 ,  H01F17/00

CPC classification number: H01L23/5227 ,  H01F17/0006 ,  H01F17/0013 ,  H01F27/2804 ,  H01F2027/2809 ,  H01L23/66 ,  H01L2223/6672 ,  H01P5/12 ,  H01P5/181

Abstract: This transformer includes primary and secondary tracks (10, 20) that are coupled to one another by mutual inductance, the primary and secondary tracks being superimposed on top of each other in two parallel planes while being arranged to follow the same contour (C), the plane of the primary track corresponding to the main conductive layer of the circuit, said layer being deposited on a substrate (30), and the secondary track being supported, plumb with the primary track, by supporting means including walls (41-46; 51-56), each wall bearing directly on the substrate and against a lower surface (24) of the secondary track (20), and having a length (L) larger than a width (I), and having a height allowing a predetermined interval to be created between an upper surface (14) of the primary track (10) and the lower surface (24) of the secondary track (20).

公开(公告)号：US09755586B2

公开(公告)日：2017-09-05

申请号：US15035561

申请日：2014-11-18

Applicant: Thales

Inventor： Jean-Philippe Plaze ,  Vincent Petit ,  Benoît Mallet-Guy

IPC: H03F1/52 ,  H03F3/19 ,  H03G7/00 ,  H03G11/00 ,  H03G11/02 ,  H03G11/06

CPC classification number: H03F1/52 ,  H03F3/19 ,  H03F2200/211 ,  H03F2200/294 ,  H03F2200/444 ,  H03F2200/451 ,  H03G7/00 ,  H03G11/00 ,  H03G11/002 ,  H03G11/02 ,  H03G11/06

Abstract: This radiofrequency power limiter includes at least one transistor, a drain of the transistor being directly connected to a mesh connecting an input to an output of the limiter, a source of the transistor being connected to a common reference potential, and a gate of the transistor being connected to a common control potential. The transistor is not biased between its drain and its source during operation of the limiter.