公开(公告)号：US11342016B2

公开(公告)日：2022-05-24

申请号：US17110624

申请日：2020-12-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gaurav Gupta ,  Zhiqiang Wu

IPC: G11C11/00 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

Abstract: In some embodiments, the present application provides a memory device. The memory device includes a first read bias transistor, a first pull-up read-enable transistor, an MTJ memory cell, a first pull-down read-enable transistor, and a first non-linear resistance device. The first non-linear resistance device is coupled in series and between the first pull-up read-enable transistor and the first read bias transistor. The first non-linear resistance device is configured to provide a first resistance when applied a first voltage and a second resistance greater than the first resistance when applied a second voltage smaller than the first voltage.

公开(公告)号：US11031544B2

公开(公告)日：2021-06-08

申请号：US16506083

申请日：2019-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gaurav Gupta ,  William J. Gallagher

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

Abstract: In some embodiments, the present application provides a memory device. The memory device includes a ferromagnetic free layer; a non-magnetic barrier layer overlying the ferromagnetic free layer; and a superparamagnetic free layer overlying the non-magnetic barrier layer.

公开(公告)号：US20200005845A1

公开(公告)日：2020-01-02

申请号：US16395571

申请日：2019-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gaurav Gupta ,  Zhiqiang Wu ,  William J. Gallagher

IPC: G11C11/16 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L27/22

Abstract: In some embodiments, the present application provides a magnetic memory device. The magnetic memory device comprises a bottom electrode, and a first synthetic anti-ferromagnetic (SyAF) layer including a first pinning layer and a second pinning layer disposed over the bottom electrode and having opposite magnetization directions and separated by a first spacer layer. The magnetic memory device further comprises a reference layer disposed over the first pair of pinning layers and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further comprises a second synthetic anti-ferromagnetic (SyAF) layer including a third pinning layer and a fourth pinning layer disposed over the free layer and having opposite magnetization directions and separated by a second spacer layer.

公开(公告)号：US12217782B2

公开(公告)日：2025-02-04

申请号：US18332674

申请日：2023-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gaurav Gupta ,  Zhiqiang Wu ,  Yih Wang

IPC: G11C11/16

Abstract: The disclosed MTJ read circuits include a current steering element coupled to the read path. At a first node of the current steering element, a proportionally larger current is maintained to meet the requirements of a reliable voltage or current sensing. At a second node of the current steering element, a proportionally smaller current is maintained, which passes through the MTJ structure. The current at the first node is proportional to the current at the second node such that sensing the current at the first node infers the current at the second node, which is affected by the MTJ resistance value.

公开(公告)号：US20220215869A1

公开(公告)日：2022-07-07

申请号：US17703869

申请日：2022-03-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gaurav Gupta ,  Zhiqiang Wu ,  Yih Wang

IPC: G11C11/16

Abstract: The disclosed MTJ read circuits include a current steering element coupled to the read path. At a first node of the current steering element, a proportionally larger current is maintained to meet the requirements of a reliable voltage or current sensing. At a second node of the current steering element, a proportionally smaller current is maintained, which passes through the MTJ structure. The current at the first node is proportional to the current at the second node such that sensing the current at the first node infers the current at the second node, which is affected by the MTJ resistance value.

公开(公告)号：US11309005B2

公开(公告)日：2022-04-19

申请号：US16655056

申请日：2019-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gaurav Gupta ,  Zhiqiang Wu ,  Yih Wang

IPC: G11C11/00 ,  G11C11/16

Abstract: The disclosed MTJ read circuits include a current steering element coupled to the read path. At a first node of the current steering element, a proportionally larger current is maintained to meet the requirements of a reliable voltage or current sensing. At a second node of the current steering element, a proportionally smaller current is maintained, which passes through the MTJ structure. The current at the first node is proportional to the current at the second node such that sensing the current at the first node infers the current at the second node, which is affected by the MTJ resistance value.

公开(公告)号：US11676648B2

公开(公告)日：2023-06-13

申请号：US17703869

申请日：2022-03-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gaurav Gupta ,  Zhiqiang Wu ,  Yih Wang

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/161

Abstract: The disclosed MTJ read circuits include a current steering element coupled to the read path. At a first node of the current steering element, a proportionally larger current is maintained to meet the requirements of a reliable voltage or current sensing. At a second node of the current steering element, a proportionally smaller current is maintained, which passes through the MTJ structure. The current at the first node is proportional to the current at the second node such that sensing the current at the first node infers the current at the second node, which is affected by the MTJ resistance value.

公开(公告)号：US11081153B2

公开(公告)日：2021-08-03

申请号：US16395571

申请日：2019-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gaurav Gupta ,  Zhiqiang Wu ,  William J. Gallagher

IPC: G11C11/16 ,  H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10

Abstract: In some embodiments, the present application provides a magnetic memory device. The magnetic memory device comprises a bottom electrode, and a first synthetic anti-ferromagnetic (SyAF) layer including a first pinning layer and a second pinning layer disposed over the bottom electrode and having opposite magnetization directions and separated by a first spacer layer. The magnetic memory device further comprises a reference layer disposed over the first pair of pinning layers and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further comprises a second synthetic anti-ferromagnetic (SyAF) layer including a third pinning layer and a fourth pinning layer disposed over the free layer and having opposite magnetization directions and separated by a second spacer layer.

公开(公告)号：US20210090631A1

公开(公告)日：2021-03-25

申请号：US17110624

申请日：2020-12-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gaurav Gupta ,  Zhiqiang Wu

IPC: G11C11/16 ,  H01L43/02 ,  H01L27/22

Abstract: In some embodiments, the present application provides a memory device. The memory device includes a first read bias transistor, a first pull-up read-enable transistor, an MTJ memory cell, a first pull-down read-enable transistor, and a first non-linear resistance device. The first non-linear resistance device is coupled in series and between the first pull-up read-enable transistor and the first read bias transistor. The first non-linear resistance device is configured to provide a first resistance when applied a first voltage and a second resistance greater than the first resistance when applied a second voltage smaller than the first voltage.