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公开(公告)号:US12293959B2
公开(公告)日:2025-05-06
申请号:US18232200
申请日:2023-08-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jian-Hong Lin , Hsin-Chun Chang , Ming-Hong Hsieh , Ming-Yih Wang , Yinlung Lu
IPC: H01L23/48 , H01L21/768 , H01L23/522 , H01L23/528
Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.
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公开(公告)号:US11616002B2
公开(公告)日:2023-03-28
申请号:US17162584
申请日:2021-01-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jian-Hong Lin , Hsin-Chun Chang , Ming-Hong Hsieh , Ming-Yih Wang , Yinlung Lu
IPC: H01L23/48 , H01L23/522 , H01L21/768 , H01L23/528
Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.
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公开(公告)号:US20180151511A1
公开(公告)日:2018-05-31
申请号:US15396909
申请日:2017-01-03
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Jian-Hong Lin , Kuo-Yen Liu , Hsin-Chun Chang , Tzu-Li Lee , Yu-Ching Lee , Yih-Ching Wang
CPC classification number: H01L23/562 , H01L21/76805 , H01L23/522 , H01L23/5226 , H01L23/585 , H01L27/0248 , H01L2224/06519 , H01L2224/09519 , H01L2224/30519 , H01L2224/33519
Abstract: A semiconductor device and a method of manufacture thereof are provided. The method for manufacturing the semiconductor device includes forming a first dielectric layer on a substrate. Next, forming a first dummy metal layer on the first dielectric layer. Then, forming a second dielectric layer over the first dummy metal layer. Furthermore, forming an opening in the second dielectric layer and the first dummy metal layer. Then, forming a dummy via in the opening, wherein the dummy via extending through the second dielectric layer and at least partially through the first dummy metal layer. Finally, forming a second dummy metal layer on the second dielectric layer and contact the dummy via.
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公开(公告)号:US10777510B2
公开(公告)日:2020-09-15
申请号:US15396909
申请日:2017-01-03
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Jian-Hong Lin , Kuo-Yen Liu , Hsin-Chun Chang , Tzu-Li Lee , Yu-Ching Lee , Yih-Ching Wang
IPC: H01L23/00 , H01L23/58 , H01L27/02 , H01L23/522 , H01L21/768
Abstract: A semiconductor device and a method of manufacture thereof are provided. The method for manufacturing the semiconductor device includes forming a first dielectric layer on a substrate. Next, forming a first dummy metal layer on the first dielectric layer. Then, forming a second dielectric layer over the first dummy metal layer. Furthermore, forming an opening in the second dielectric layer and the first dummy metal layer. Then, forming a dummy via in the opening, wherein the dummy via extending through the second dielectric layer and at least partially through the first dummy metal layer. Finally, forming a second dummy metal layer on the second dielectric layer and contact the dummy via.
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公开(公告)号:US10431541B2
公开(公告)日:2019-10-01
申请号:US15463105
申请日:2017-03-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jian-Hong Lin , Hsin-Chun Chang , Hui Lee , Yung-Sheng Huang , Yung-Huei Lee
IPC: G06F17/50 , H01L27/02 , H01L23/522 , H01L23/528
Abstract: A semiconductor device for fabricating an IC is provided. The semiconductor device includes an interconnect structure and a first conductive line. The interconnect structure is made of conductive material and includes a first interconnect portion and a second interconnect portion. The second interconnect portion is connected to a first end of the first interconnect portion, and a width of the second interconnect portion is less than a width of the first interconnect portion. The first conductive line is arranged over or below the first interconnect portion and providing an electrical connection between the interconnect structure and an electrical structure. A distance between the first conductive line and the first end is less than a distance between the first conductive line and a second end of the first interconnect portion which is opposite to the first end.
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公开(公告)号:US12243805B2
公开(公告)日:2025-03-04
申请号:US17815997
申请日:2022-07-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jian-Hong Lin , Hsin-Chun Chang , Ming-Hong Hsieh , Ming-Yih Wang , Yinlung Lu
IPC: H01L23/48 , H01L21/768 , H01L23/522 , H01L23/528
Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.
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公开(公告)号:US11955441B2
公开(公告)日:2024-04-09
申请号:US17706039
申请日:2022-03-28
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Jian-Hong Lin , Kuo-Yen Liu , Hsin-Chun Chang , Tzu-Li Lee , Yu-Ching Lee , Yih-Ching Wang
IPC: H01L23/00 , H01L23/522 , H01L23/58 , H01L27/02 , H01L21/768
CPC classification number: H01L23/562 , H01L23/522 , H01L23/5226 , H01L23/585 , H01L27/0248 , H01L21/76805 , H01L2224/06519 , H01L2224/09519 , H01L2224/30519 , H01L2224/33519
Abstract: An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.
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公开(公告)号:US20220367323A1
公开(公告)日:2022-11-17
申请号:US17815997
申请日:2022-07-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jian-Hong Lin , Hsin-Chun Chang , Ming-Hong Hsieh , Ming-Yih Wang , Yinlung Lu
IPC: H01L23/48 , H01L23/522 , H01L21/768 , H01L23/528
Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.
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9.
公开(公告)号:US11302654B2
公开(公告)日:2022-04-12
申请号:US17018381
申请日:2020-09-11
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Jian-Hong Lin , Kuo-Yen Liu , Hsin-Chun Chang , Tzu-Li Lee , Yu-Ching Lee , Yih-Ching Wang
IPC: H01L21/768 , H01L23/00 , H01L23/58 , H01L27/02 , H01L23/522
Abstract: A method includes depositing a first dielectric layer over a substrate; forming a first dummy metal layer over the first dielectric layer, wherein the first dummy metal layer has first and second portions laterally separated from each other; depositing a second dielectric layer over the first dummy metal layer; etching an opening having an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first dummy metal layer, and a lower portion in the first dielectric layer, wherein a width of the lower portion of the opening is greater than a width of the middle portion of the opening, and a bottom of the opening is higher than a bottom of the first dielectric layer; and forming a dummy via in the opening and a second dummy metal layer over the dummy via and the second dielectric layer.
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