公开(公告)号：US20090184983A1

公开(公告)日：2009-07-23

申请号：US12320051

申请日：2009-01-15

申请人： Takashi Nose ,  Hirobumi Furihata ,  Yoshihiko Hori ,  Hiroshi Tsuchi

发明人： Takashi Nose ,  Hirobumi Furihata ,  Yoshihiko Hori ,  Hiroshi Tsuchi

IPC分类号： G09G5/10

CPC分类号： G09G5/04 ,  G09G3/2059 ,  G09G3/3688 ,  G09G2310/0297 ,  G09G2340/0407

摘要： A display apparatus includes a display panel; and a display panel driver configured to drive signal lines of the display panel. The display panel driver includes: a color reducing circuit configured to be possible to generate a first color reduction image data from a first input image data by executing an error diffusion process by using a first error value, and to generate a second color reduction image data from the first input image data by executing the error diffusion process by using a second error value which is different from the first error value; and a driving section configured to drive a first pixel positioned on a horizontal line of the display panel in response to the first color reduction image data, and drive a second pixel positioned on the horizontal line and adjacent to a the first pixel in a horizontal direction, in response to the second color reduction image data.

摘要翻译： 显示装置包括显示面板; 以及配置成驱动显示面板的信号线的显示面板驱动器。 显示面板驱动器包括：颜色降低电路，被配置为可以通过使用第一误差值执行误差扩散处理从第一输入图像数据生成第一降色图像数据，并且生成第二降色图像数据 通过使用与第一误差值不同的第二误差值来执行误差扩散处理从第一输入图像数据中获取第一输入图像数据; 以及驱动部，被配置为响应于所述第一减色图像数据来驱动位于所述显示面板的水平线上的第一像素，并且驱动位于所述水平线上并与所述第一像素在水平方向相邻的第二像素 响应于第二降色图像数据。

公开(公告)号：US08355032B2

公开(公告)日：2013-01-15

申请号：US12320051

申请日：2009-01-15

申请人： Takashi Nose ,  Hirobumi Furihata ,  Yoshihiko Hori ,  Hiroshi Tsuchi

发明人： Takashi Nose ,  Hirobumi Furihata ,  Yoshihiko Hori ,  Hiroshi Tsuchi

IPC分类号： G09G3/36 ,  G09G5/10 ,  G09G5/02 ,  G06K9/32

CPC分类号： G09G5/04 ,  G09G3/2059 ,  G09G3/3688 ,  G09G2310/0297 ,  G09G2340/0407

摘要： A display apparatus includes a display panel; and a display panel driver configured to drive signal lines of the display panel. The display panel driver includes: a color reducing circuit configured to be possible to generate a first color reduction image data from a first input image data by executing an error diffusion process by using a first error value, and to generate a second color reduction image data from the first input image data by executing the error diffusion process by using a second error value which is different from the first error value; and a driving section configured to drive a first pixel positioned on a horizontal line of the display panel in response to the first color reduction image data, and drive a second pixel positioned on the horizontal line and adjacent to a the first pixel in a horizontal direction, in response to the second color reduction image data.

公开(公告)号：US08687027B2

公开(公告)日：2014-04-01

申请号：US13618174

申请日：2012-09-14

申请人： Takashi Nose ,  Hirobumi Furihata ,  Yoshihiko Hori ,  Hiroshi Tsuchi

发明人： Takashi Nose ,  Hirobumi Furihata ,  Yoshihiko Hori ,  Hiroshi Tsuchi

IPC分类号： G09G3/36 ,  G09G5/10 ,  G09G5/02 ,  G06K9/32

CPC分类号： G09G5/04 ,  G09G3/2059 ,  G09G3/3688 ,  G09G2310/0297 ,  G09G2340/0407

摘要： A display panel driver includes a color reducing circuit and a driving section. The driving section is configured to drive a first pixel and a second pixel. If a second input image data and a third input image data corresponding to the second pixel are supplied as an image data of a second image display format, then the color reducing circuit generates a third color reduction image data and a fourth color reduction image data. If the first input image data is supplied as the image data of the first image display format, then the first selector selects the third error value, and if the second input image data and the third input image data are supplied as the image data of the second image display format, then the first selector selects the second error value.

摘要翻译： 显示面板驱动器包括减色电路和驱动部。 驱动部分被配置为驱动第一像素和第二像素。 如果将与第二像素相对应的第二输入图像数据和第三输入图像数据作为第二图像显示格式的图像数据提供，则颜色降低电路产生第三降色图像数据和第四降色图像数据。 如果第一输入图像数据作为第一图像显示格式的图像数据提供，则第一选择器选择第三误差值，并且如果第二输入图像数据和第三输入图像数据被提供为 第二图像显示格式，则第一选择器选择第二误差值。

公开(公告)号：US20130241963A1

公开(公告)日：2013-09-19

申请号：US13618174

申请日：2012-09-14

申请人： Takahashi Nose ,  Hirobumi Furihata ,  Yoshihiko Hori ,  Hiroshi Tsuchi

发明人： Takahashi Nose ,  Hirobumi Furihata ,  Yoshihiko Hori ,  Hiroshi Tsuchi

IPC分类号： G09G5/04

CPC分类号： G09G5/04 ,  G09G3/2059 ,  G09G3/3688 ,  G09G2310/0297 ,  G09G2340/0407

摘要： A display panel driver includes a color reducing circuit and a driving section. The driving section is configured to drive a first pixel and a second pixel. If a second input image data and a third input image data corresponding to the second pixel are supplied as an image data of a second image display format, then the color reducing circuit generates a third color reduction image data and a fourth color reduction image data. If the first input image data is supplied as the image data of the first image display format, then the first selector selects the third error value, and if the second input image data and the third input image data are supplied as the image data of the second image display format, then the first selector selects the second error value.

摘要翻译： 显示面板驱动器包括减色电路和驱动部。 驱动部分被配置为驱动第一像素和第二像素。 如果将与第二像素相对应的第二输入图像数据和第三输入图像数据作为第二图像显示格式的图像数据提供，则颜色降低电路产生第三降色图像数据和第四降色图像数据。 如果第一输入图像数据作为第一图像显示格式的图像数据提供，则第一选择器选择第三误差值，并且如果第二输入图像数据和第三输入图像数据被提供为 第二图像显示格式，则第一选择器选择第二误差值。

公开(公告)号：US06552706B1

公开(公告)日：2003-04-22

申请号：US09619307

申请日：2000-07-19

申请人： Naoyasu Ikeda ,  Hidenori Ikeno ,  Hiroshi Tsuchi ,  Takashi Nose

发明人： Naoyasu Ikeda ,  Hidenori Ikeno ,  Hiroshi Tsuchi ,  Takashi Nose

IPC分类号： G09G336

CPC分类号： G09G3/3607 ,  G09G3/3614 ,  G09G3/3648 ,  G09G2300/0452 ,  G09G2310/0205 ,  G09G2320/0247

摘要： An active matrix type liquid crystal display apparatus can reduce occurrence of flicker, which can be a cause of degradation of picture quality even in a particular fixed pattern, by using a data driver circuit constantly inverting polarity of voltage of adjacent outputs. The active matrix type liquid crystal display apparatus has display picture elements, each consisting of four pixels of first to four pixels arranged vertically and horizontally per two, scanning lines, each being in common for the four pixels, data lines arranged per two on opposite sides of vertically aligned two pixels, a common electrode being common for the four pixels, and a data driver circuit for writing voltages from the datalines simultaneously for the four pixels of each picture element when the one scanning line is selected. The pixels are located at the same position in laterally adjacent picture elements being connected to data lines at different sides relative to each other. The data driver circuit is controlled to apply different polarities of voltages to adjacent data lines with respect to a voltage for the common electrode, and to invert polarities of the voltages to be applied to respective data lines with respect to the voltage of the common electrode when the scanning line is selected.

摘要翻译： 有源矩阵型液晶显示装置可以通过使用持续颠倒相邻输出的电压的极性的数据驱动器电路来减少闪烁的发生，这可能是特定固定图案中的图像质量劣化的原因。 有源矩阵型液晶显示装置具有显示图像元素，每个由每两个垂直和水平排列的第一至四个像素的四个像素组成，每个四个像素共同的扫描线，相对两侧布置的数据线 垂直排列的两个像素的公共电极，四个像素共用的公共电极，以及数据驱动器电路，用于当选择一条扫描线时同时为每个像素的四个像素写入数据的电压。 像素位于相邻的相邻图像元素的相同位置处，其相对于彼此在不同侧被连接到数据线。 控制数据驱动器电路以相对于公共电极的电压施加相邻数据线的不同极性的电压，并且相对于公共电极的电压将施加到相应数据线的电压的极性反转，当 选择扫描线。

公开(公告)号：US09224356B2

公开(公告)日：2015-12-29

申请号：US14002948

申请日：2012-03-01

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： H03M1/00 ,  G09G5/00 ,  H03M1/66 ,  G09G3/32 ,  G09G3/36 ,  H03M1/76

CPC分类号： G09G5/003 ,  G09G3/3291 ,  G09G3/3688 ,  G09G3/3696 ,  G09G5/00 ,  G09G2310/027 ,  G09G2310/0291 ,  H03M1/661 ,  H03M1/76

摘要： DAC includes a decoder that receives N number of reference voltages and an n-bit digital signal (n 4) to select first to third voltages, and an operational amplifier to output (first voltage+second voltage+2 third voltage)/4 voltage. The operational amplifier is able to output, for respective 2^n combinations of the n-bit digital signal, voltage levels from an Ath level, as a base level, to an (A−1+2^n)th level. The N number of reference voltages include Ath level, (A+4)th level, (A−4+2^n) and (A+2^n), and an at most {−4+2^(n−2)} reference voltages obtained by decimating a pre-set at least one reference voltage from {−3+2^(n−2)} reference voltages that are other than the four number of reference voltages from the {1+2^(n−2)} reference voltages corresponding to the voltage levels spaced each other at an interval of 4 levels from the Ath level. N is not less than 4 and not more than 2^(n−2).

摘要翻译： DAC包括接收N个参考电压的解码器和用于选择第一至第三电压的n位数字信号（n4），以及输出（第一电压+第二电压+2第三电压）/ 4电压的运算放大器。 对于n位数字信号的相应2 ^ n组合，运算放大器能够从作为基准电平的Ath电平到（A-1 + 2 ^ n）级的电压电平输出。 N个参考电压包括Ath电平，（A + 4）电平，（A-4 + 2 ^ n）和（A + 2 ^ n），以及至多{-4 + 2 ^（n-2） ）}参考电压，其通过从{1 + 2 ^（n-2）}个参考电压除去来自{1 + 2 ^（n-2）}的四个参考电压以外的预设的至少一个参考电压而获得 -2）}相对应的电压电平的参考电压以与Ath级别成4级的间隔彼此隔开。 N不小于4且不大于2 ^（n-2）。

公开(公告)号：US08786479B2

公开(公告)日：2014-07-22

申请号：US13064354

申请日：2011-03-21

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： H03M1/68

CPC分类号： G09G3/3688 ,  G09G3/3696 ,  G09G2310/027 ,  G09G2330/028

摘要： Reference voltages of a reference voltage ensemble are classed into first to (z×S+1)th reference voltage groups, where S is a power of 2 inclusive of 1 and z is a power of 2 plus 1. A decoder includes first to (z×S+1)th sub-decoders provided in association with the first to (z×S+1)th reference voltage groups, and a (z×S+1) input and 2 output type sub-decoder. The first to (z×S+1)th sub-decoders select, from the reference voltage of the first to the (z×S+1)th reference voltage groups, those reference voltages allocated to columns in a two-dimensional array of the reference voltages associated with the values of a first bit group of an input digital signal. The (z×S+1) input and 2 output sub-decoder receives outputs of the first to (z×S+1)th sub-decoders to select the first and second voltages from the reference voltages selected by the first to (z×S+1)th sub-decoders in response to the value of a second bit group of the input digital signal. An interpolation circuit receives the first and second voltages, selected by the decoder, to output a voltage level obtained on interpolation with an interpolation ratio of 1:1 (FIG. 1).

摘要翻译： 参考电压集合的参考电压被分类为第一至第（z×S + 1）个参考电压组，其中S是2的功率，包括1，z是2加1的功率。解码器包括首先（ 和第（z×S + 1）个输入型子解码器相关联地设置的z×S + 1个子解码器。 第一至第（Z×S + 1）子解码器从第一至第（z×S + 1）个参考电压组的参考电压中选择分配给二维阵列中的列的参考电压 与输入数字信号的第一位组的值相关联的参考电压。 （z×S + 1）输入和2输出子解码器接收第一至第（Z×S + 1）个子解码器的输出，以从由第一至第（z） ×S + 1）个子解码器，响应于输入数字信号的第二位组的值。 接收由解码器选择的第一和第二电压的插值电路，以1：1（图1）的插值比率输出以内插获得的电压电平。

公开(公告)号：US08686987B2

公开(公告)日：2014-04-01

申请号：US13029888

申请日：2011-02-17

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/0291 ,  G09G2320/0252 ,  G09G2330/021

摘要： Disclosed is an output circuit including a differential amplifier stage, an output amplifier stage, an amplification acceleration circuit and a capacitance connection control circuit. The output amplifier stage includes push/pull type transistors connected an output terminal. The amplification acceleration circuit includes a first switch and a first transistor, connected between a first output of the differential amplifier stage and the output terminal, and a second transistor and a second switch connected between the output terminal and a second output of the differential amplifier stage. The capacitance connection control circuit includes first capacitive element having first end connected to the output terminal, a first switch connected between a second end of the first capacitive element and a first voltage supply terminal, and a second switch connected between the second end of the first capacitive element and one output of a first differential pair of the differential amplifier stage.

摘要翻译： 公开了一种包括差分放大级，输出放大级，放大加速电路和电容连接控制电路的输出电路。 输出放大级包括连接有输出端的推/拉型晶体管。 放大加速电路包括连接在差分放大器级的第一输出端和输出端子之间的第一开关和第一晶体管，以及连接在差分放大器级的输出端子和第二输出端之间的第二晶体管和第二开关 。 电容连接控制电路包括第一电容元件，第一电容元件具有连接到输出端子的第一端子，连接在第一电容元件的第二端和第一电压供应端子之间的第一开关和连接在第一电容元件的第二端之间的第二开关 电容元件和差分放大器级的第一差分对的一个输出。

公开(公告)号：US08400207B2

公开(公告)日：2013-03-19

申请号：US12847339

申请日：2010-07-30

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： H03L5/00

CPC分类号： G09G3/20 ,  G09G2310/027 ,  G09G2310/0289 ,  H03K19/018521

摘要： A level shift circuit includes a first circuit connected between a first power supply terminal (PST) and an output terminal (OT) of the level shift circuit to set OT to a first voltage (V1) when conducting, a second circuit connected between a second PST and OT to set OT to the second voltage (V2) when conducting, and a third circuit that receives an input signal and a feedback signal from OT so that, when OT=V2 and input=a third voltage (V3), the first circuit conducts, and when OT=V1, the first circuit is made nonconductive irrespective of the value of the input signal. The second circuit is made conductive and nonconductive, when the input=a fourth voltage (V4) and V3, respectively. A high/low relationship of V1, V2=that of V3, V4. The input between V3, V4 has a lower amplitude than the output signal between V1, V2.

摘要翻译： 电平移位电路包括连接在电平移位电路的第一电源端子（PST）和输出端子（OT）之间的第一电路，用于在导通时将OT设置为第一电压（V1），第二电路连接在第二电源 PST和OT将OT设置为第二电压（V2）;以及第三电路，其从OT接收输入信号和反馈信号，使得当OT = V2和输入=第三电压（V3）时，第一电路 电路导通，并且当OT = V1时，不管输入信号的值如何，第一电路都是不导通的。 当输入分别为第四电压（V4）和V3时，第二电路导通和不导通。 V1，V2的高低关系为V3，V4。 V3，V4之间的输入幅度比V1，V2之间的输出信号低。

公开(公告)号：US07872499B2

公开(公告)日：2011-01-18

申请号：US12320778

申请日：2009-02-04

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： H03K19/0175 ,  H03L5/00

CPC分类号： H03K19/018521 ,  G09G3/20 ,  G09G3/3208 ,  G09G3/3611 ,  G09G2310/0289 ,  H03K19/0013 ,  H03K19/01707

摘要： Disclosed is a level shift circuit that includes a first level shifter which is connected between an output terminal and a first power supply terminal that supplies a first voltage and sets the output terminal to a level of the first voltage when an input signal received at an input terminal assumes a first value; a second level shifter which is connected between the output terminal and a second power supply terminal that supplies a second voltage and sets the output terminal to a level of the second voltage when the input signal assumes a complementary value of the first value; and a feedback control unit that performs control of deactivating the first level shifter during a predetermined time interval including a point of time when the input signal is supplied when it is detected that the output terminal immediately before the input signal is received at the input terminal assumes the first voltage level. When the input signal supplied in the predetermined time interval assumes a value that sets the output terminal to the second voltage level, the second level shifter sets the output terminal to the second voltage level with the first level shifter deactivated.

摘要翻译： 公开了一种电平移位电路，其包括第一电平移位器，其连接在输出端子和提供第一电压的第一电源端子之间，并且当在输入端接收的输入信号时将输出端子设置为第一电压的电平 终端假设第一个值; 第二电平移位器，连接在输出端和提供第二电压的第二电源端之间，当输入信号呈现第一值的互补值时，将输出端设置为第二电压的电平; 以及反馈控制单元，其在包括当检测到在输入端子处接收到输入信号之前的输出端子被假定时提供输入信号的时间点的预定时间间隔期间，执行停用第一电平移位器的控制， 第一个电压电平。 当在预定时间间隔内提供的输入信号采取将输出端子设置为第二电压电平的值时，第二电平移位器将第一电平移位器的输出端子设置为第二电压电平。