公开(公告)号：US5706102A

公开(公告)日：1998-01-06

申请号：US400814

申请日：1995-03-08

申请人： Takuji Okumura ,  Hideo Azumai ,  Satoshi Iwatsubo

发明人： Takuji Okumura ,  Hideo Azumai ,  Satoshi Iwatsubo

IPC分类号： G06T3/40 ,  G06T5/00 ,  H04N1/393 ,  H04N1/40 ,  H04N1/405 ,  H04N1/00

CPC分类号： H04N1/3935 ,  G06T3/40

摘要： A data managing device according to the present invention processes the same object pixel before and after variable magnification processing, and collectively manages processing data before and after the variable magnification processing by making access to a memory once. In the variable magnification processing before and after which the number of object pixels differs, 1-bit BF data for area separation processing performed before the variable magnification processing and 7-bit produced error data for error diffusion processing performed after the variable magnification processing are mixed, and data composed of a total of 8 bits which is obtained by the mixing is read out/written from and to the same address in a SRAM 4 at the same access timing. Therefore, at the time of reduction processing, a reduction processing control signal SMWAIT is produced, and error diffusion processing is stopped when the signal is at a high level.

摘要翻译： 根据本发明的数据管理装置在可变放大处理之前和之后处理相同的对象像素，并且通过访问存储器一次来共同管理可变放大处理之前和之后的处理数据。 在可变倍率处理之前，目标像素的数量不同，在可变倍率处理之前执行的用于区域分离处理的1位BF数据和在可变倍率处理之后执行的用于误差扩散处理的7位产生误差数据混合 ，并且通过混合获得的总共8位组成的数据在SRAM 4中以相同的访问定时被读出/写入同一地址。 因此，在缩小处理时，产生缩小处理控制信号SMWAIT，当信号为高电平时，停止误差扩散处理。

公开(公告)号：US5659402A

公开(公告)日：1997-08-19

申请号：US367846

申请日：1995-01-03

申请人： Hiroyuki Fujita ,  Ariyoshi Hikosaka ,  Tetsuji Kajitani ,  Hidemitsu Hirano ,  Takuji Okumura ,  Tsukasa Matsushita ,  Hideo Azumai ,  Satoshi Iwatsubo

发明人： Hiroyuki Fujita ,  Ariyoshi Hikosaka ,  Tetsuji Kajitani ,  Hidemitsu Hirano ,  Takuji Okumura ,  Tsukasa Matsushita ,  Hideo Azumai ,  Satoshi Iwatsubo

IPC分类号： H04N1/40

CPC分类号： H04N1/40062

摘要： In accordance with the present invention, a quadratic differential values is first calculated, based on differences in the density data between an object pixel and respective peripheral pixels around the object pixel. The square value SS of the quadratic differential value S and the sum .SIGMA.SS obtained by adding up the square values SS of quadratic differential values for continuous five pixels are employed as determination values (step n1). The square sum .SIGMA.SS is compared with respective threshold values a, b and d, and the square value SS is compared with respective threshold values c, e and f (steps n2 to n6 and n8). Based on these comparison results, it is judged which image area among a character image area, gray-scale image area and dotted image area the object pixel belongs to. As for the image area judgement concerning the dotted image area, the final judgement that the object pixel belongs to the dotted image area is made only when nine continuous pixels including the object pixel are all judged to belong to the dotted image area. Since the square values SS and square sum .SIGMA.SS take only a positive value, the threshold values are set only in a positive range, and hence the image processing can be simplified. Further, by employing the square sum .SIGMA.SS, the states of the peripheral pixels can be taken into consideration for the image area judgement.

摘要翻译： 根据本发明，首先基于对象像素与对象像素周围的相应周边像素之间的浓度数据的差异，首先计算二次微分值。 采用二次微分值S的平方值SS和通过将连续5个像素的二次微分值的平方值SS相加得到的总和SIGMA SS作为确定值（步骤n1）。 将平方和SIGMA SS与相应的阈值a，b和d进行比较，并将平方值SS与相应的阈值c，e和f进行比较（步骤n2至n6和n8）。 基于这些比较结果，判断对象像素所属的字符图像区域，灰度图像区域和虚线图像区域中的哪个图像区域。 对于关于虚线图像区域的图像区域判断，仅当包括对象像素的九个连续像素都被判断为属于虚线图像区域时，仅进行对象像素属于虚线图像区域的最终判断。 由于平方值SS和平方和SIGMA SS仅取正值，所以仅在正的范围内设定阈值，因此能够简化图像处理。 此外，通过采用平方和SIGMA SS，可以考虑周边像素的状态用于图像区域判断。

公开(公告)号：US5349449A

公开(公告)日：1994-09-20

申请号：US86906

申请日：1993-07-07

申请人： Ikuhiro Omi ,  Hideo Azumai ,  Satoshi Iwatsubo

发明人： Ikuhiro Omi ,  Hideo Azumai ,  Satoshi Iwatsubo

IPC分类号： G06F13/362 ,  G06F12/00 ,  G06F15/16 ,  G06F15/177 ,  G06T1/20 ,  H04N1/21 ,  H04N1/32 ,  H04N1/40

CPC分类号： H04N1/32443 ,  H04N1/00915 ,  H04N1/32358 ,  H04N2201/3294 ,  H04N2201/3297

摘要： A circuit according to the present invention has an input image processing circuit 11 and an image output processing circuit 12 which are asynchronously operated and a shared memory 18. In addition, it has a memory access signal switching circuit 110. The input image processing circuit 11 and the image output processing circuit 12 access the memory 18 in synchronization with the same memory access synchronous clock SYSCLK, and the access right of the image output processing circuit 12 precedes the access right of the input image processing circuit 11. If one cycle of the processing operation of the input image processing circuit 11 is set longer than the sum of the maximum time period during which the input image processing circuit 11 accesses the memory 18 and the maximum time period during which the image output processing circuit 12 accesses the memory 18, the access to the memory 18 by the input image processing circuit 11 and the access to the memory by the image output processing circuit 12 are not overlapped with each other.

摘要翻译： 根据本发明的电路具有异步操作的输入图像处理电路11和图像输出处理电路12以及共享存储器18.此外，它具有存储器访问信号切换电路110.输入图像处理电路11 并且图像输出处理电路12与同一个存储器访问同步时钟SYSCLK同步地访问存储器18，并且图像输出处理电路12的访问权在输入图像处理电路11的访问权限之前。如果一个周期的 输入图像处理电路11的处理操作被设置为长于输入图像处理电路11访问存储器18的最大时间段和图像输出处理电路12访问存储器18的最大时间段之和， 由输入图像处理电路11访问存储器18，并通过图像输出处理访问存储器 电路12不重叠。

公开(公告)号：US5532827A

公开(公告)日：1996-07-02

申请号：US89332

申请日：1993-07-12

申请人： Tetsuji Kajitani ,  Ariyoshi Hikosaka ,  Hideo Azumai ,  Satoshi Iwatsubo

发明人： Tetsuji Kajitani ,  Ariyoshi Hikosaka ,  Hideo Azumai ,  Satoshi Iwatsubo

IPC分类号： H04N1/405 ,  H04N1/407 ,  H04N1/41 ,  H04N1/40 ,  G01D15/14

CPC分类号： H04N1/407 ,  H04N1/4051

摘要： Partial images each constituting a predetermined matrix are sequentially taken out, and density data corresponding to pixels constituting the matrix are subjected to correction. The correction of the density data is so made as to respectively add density correcting values predetermined to correspond to pixel positions in the matrix to the density data. Consequently, the density data corresponding to the pixels constituting the matrix are considerably varied. Therefore, in a binary image obtained by subjecting the partial image constituting the matrix to halftone processing, the density of a document image is sufficiently reproduced.

摘要翻译： 依次取出构成预定矩阵的部分图像，对与构成矩阵的像素对应的浓度数据进行校正。 这样进行密度数据的校正，以分别将与矩阵中的像素位置相对应地预定的浓度校正值分别加到密度数据上。 因此，与构成矩阵的像素对应的密度数据显着变化。 因此，在构成矩阵的部分图像进行半色调处理的二值图像中，文档图像的浓度被充分地再现。

公开(公告)号：US5572337A

公开(公告)日：1996-11-05

申请号：US358542

申请日：1992-12-14

申请人： Tetsuji Kajitani ,  Ariyoshi Hikosaka ,  Hideo Azumai ,  Satoshi Iwatsubo

发明人： Tetsuji Kajitani ,  Ariyoshi Hikosaka ,  Hideo Azumai ,  Satoshi Iwatsubo

IPC分类号： H04N1/401 ,  G06T1/00 ,  H04N1/407 ,  H04N1/40

CPC分类号： H04N1/4076

摘要： Data ID obtained by making analog-to-digital conversion of an output of an image sensor or the like is subjected to shading correction, to obtain correction data SOUT. The correction data SOUT is found by the following equation using white reference data WST and black reference data BST: ##EQU1## where K is a coefficient.

摘要翻译： 通过对图像传感器等的输出进行模数转换而获得的数据ID进行阴影校正，以获得校正数据SOUT。 校正数据SOUT由以下等式使用白色参考数据WST和黑色参考数据BST：，其中K是系数。

公开(公告)号：US5519509A

公开(公告)日：1996-05-21

申请号：US367832

申请日：1995-01-03

申请人： Ariyoshi Hikosaka ,  Tetsuji Kajitani ,  Hideo Azumai ,  Satoshi Iwatsubo

发明人： Ariyoshi Hikosaka ,  Tetsuji Kajitani ,  Hideo Azumai ,  Satoshi Iwatsubo

IPC分类号： G06T5/00 ,  H04N1/403 ,  H04N1/405 ,  H04N1/407

CPC分类号： H04N1/4052 ,  H04N1/407

摘要： The present invention provides a half-tone image processing method utilizing an error diffusion technique which allows for the density adjustment of a half-tone image to be reproduced. When the density of an object pixel is converted into binary-coded data, a binary-coding object value is first calculated by adding a density value of the object pixel to an error sum of binary-coding errors distributed to the object pixel from peripheral pixels around the object pixel. Then, the binary-coding object value is compared with a threshold value TH for judging whether the object pixel is a black pixel or a white pixel. The binary-coding object value is also compared with a reference value GSLVB or GSLVW which can be variably set for the calculation of a binary-coding error HG of the object pixel. The level of the binary-coding error HG can be adjusted by variably setting the reference values GSLVB and GSLVW. Thus, the density adjustment of a half-tone image can be realized.

摘要翻译： 本发明提供了利用允许再现半色调图像的浓度调整的误差扩散技术的半色调图像处理方法。 当将对象像素的密度转换为二进制编码数据时，首先通过将对象像素的浓度值与从周边像素分配给对象像素的二进制编码错误的误差和相加来计算二进制编码对象值 围绕物体像素。 然后，将二进制编码对象值与用于判断对象像素是黑色像素还是白色像素的阈值TH进行比较。 二进制编码对象值也与可以可变地设置用于计算对象像素的二进制编码错误HG的参考值GSLVB或GSLVW进行比较。 可以通过可变地设置参考值GSLVB和GSLVW来调整二进制编码错误HG的电平。 因此，可以实现半色调图像的浓度调整。

公开(公告)号：US5646745A

公开(公告)日：1997-07-08

申请号：US89327

申请日：1993-07-12

申请人： Tetsuji Kajitani ,  Ariyoshi Hikosaka ,  Hideo Azumai ,  Satoshi Iwatsubo

发明人： Tetsuji Kajitani ,  Ariyoshi Hikosaka ,  Hideo Azumai ,  Satoshi Iwatsubo

IPC分类号： G06T1/20 ,  H04N1/40 ,  G06F12/00 ,  H01J1/00

CPC分类号： G06T1/20 ,  H04N1/40

摘要： An image data processing apparatus for performing processing using data corresponding to a plurality of lines which correspond to a plurality of scanning lines at the time of reading an image. For example, when processing is performed using data corresponding to three lines, that is, the present line, a line one ahead of the present line and a line two lines ahead of the present line, a line memory having a capacity of two lines is used. When the data corresponding to the line two lines ahead of the present line are read out from the memory, the data corresponding to the present line are written to storage locations from which the data have been read out. Consequently, it is possible to perform processing using data corresponding to three lines using a line memory having a capacity for two lines.

摘要翻译： 一种图像数据处理装置，用于在读取图像时使用与多条扫描线对应的多条线对应的数据进行处理。 例如，当使用与三条线对应的数据进行处理时，即当前行，当前行之前的一行和当前行之前两行的行，具有两行容量的行存储器是 用过的。 当从存储器中读出对应于当前行前面两行的数据的数据时，将与当前行相对应的数据写入已读出数据的存储位置。 因此，可以使用具有两行容量的行存储器来执行使用与三行对应的数据的处理。

公开(公告)号：US5764816A

公开(公告)日：1998-06-09

申请号：US788564

申请日：1997-01-24

申请人： Takashi Kohno ,  Hiroyuki Fujita ,  Hideo Azumai ,  Satoshi Iwatsubo

发明人： Takashi Kohno ,  Hiroyuki Fujita ,  Hideo Azumai ,  Satoshi Iwatsubo

IPC分类号： H04N1/387 ,  G06T3/40 ,  H04N1/40

CPC分类号： G06T3/40 ,  H04N1/40068

摘要： According to the image processing apparatus of the present invention, image data are entered with an input resolution of 16 dots/mm, yet allowing the use of a conventional image processing system with a resolution of 8 dots/mm, and there can be produced an image better in quality than a conventional one. First, pixel data with an input resolution of 16 dots/mm are subjected to resolution conversion using a resolution converting unit 21. The resolution conversion is made by an odd-numbered pixel thinning processing when the apparatus mode is set to a binary mode, and by a two pixel averaging processing when the apparatus mode is set to a half-tone mode. Then, pixel data of which resolution has been converted into 8 dots/mm, are supplied to an image processing unit 22, where an image processing is then executed on the pixel data.

摘要翻译： 根据本发明的图像处理装置，以16点/ mm的输入分辨率输入图像数据，但是允许使用具有8点/ mm的分辨率的常规图像处理系统，并且可以产生 图像质量比常规图像更好。 首先，使用分辨率转换单元21对具有16点/ mm的输入分辨率的像素数据进行分辨率转换。当设备模式被设置为二进制模式时，通过奇数像素细化处理进行分辨率转换，以及 当设备模式被设置为半色调模式时，通过两像素平均处理。 然后，分辨率已被转换成8点/ mm的像素数据被提供给图像处理单元22，然后对像素数据执行图像处理。

公开(公告)号：US5198757A

公开(公告)日：1993-03-30

申请号：US731975

申请日：1991-07-18

申请人： Hideo Azumai

发明人： Hideo Azumai

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F11/22 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04

CPC分类号： G01R31/318516 ,  G06F11/2273

摘要： An apparatus for testing a semiconductor integrated circuit by using probe lines and sense lines, has a selection device for applying a selective signal in sequence to one of the probe lines, and electronic switch devices incorporated in the integrated circuit so that the electronic switch devices and intersections, where the probe lines and sense lines intersect each other, are in one-to-one correspondence and the electronic switch devices can feed signals to their corresponding sense lines in response to selective signals applied to the probe lines. Each electronic switch device is connected to test points in the integrated circuit and connected to its corresponding sense line. Many level quantization devices are provided for generating many-level quantized signal, corresponding to one of combinations of binary signals on the test points connected to the electronic switches of each electronic switch device, to its corresponding sense line, and two-level quantization devices convert the many-level quantized signal, generated on each sense line, to reproduced binary signals corresponding to the one of combinations of the binary signals on the test points.

摘要翻译： 一种用于通过使用探针线和检测线测试半导体集成电路的装置具有选择装置，用于依次将选择性信号施加到探针线之一以及并入集成电路中的电子开关装置，使得电子开关装置和 探针线和检测线彼此相交的交叉点是一一对应的，并且电子开关装置可以响应于施加到探针线的选择信号将信号馈送到它们对应的检测线。 每个电子开关装置连接到集成电路中的测试点并连接到其对应的感测线。 提供了许多级量化装置，用于产生对应于连接到每个电子开关装置的电子开关的测试点上的二进制信号的组合中的一个的多级量化信号到其对应的感测线，并且两级量化装置转换 在每个感测线上产生的多级量化信号对应于测试点上的二进制信号的组合之一的再现二进制信号。

公开(公告)号：US4855803A

公开(公告)日：1989-08-08

申请号：US224268

申请日：1988-07-26

申请人： Hideo Azumai ,  Koichi Fujii ,  Takashi Seigenji ,  Keiichi Yoshioka

发明人： Hideo Azumai ,  Koichi Fujii ,  Takashi Seigenji ,  Keiichi Yoshioka

IPC分类号： H01L27/118

CPC分类号： H01L27/118

摘要： A selectively definable semiconductor device is provided. In one form, a composite gate array includes a plurality of logic dedicated general purpose cell regions and a plurality of function dedicated cell regions each of which is disposed between the two corresponding ones of the plurality of logic dedicated general purpose cell regions, whereby each of the cell regions may be used as an interconnection region selectively. In another form, a semiconductor memory device which may be selectively defined as a ROM or a RAM by a metalization process is provided.

摘要翻译： 提供了一种选择性定义的半导体器件。 在一种形式中，复合门阵列包括多个逻辑专用通用单元区域和多个功能专用单元区域，每个单元区域设置在多个逻辑专用通用单元区域中的两个相应的逻辑专用单元区域之间， 可以选择性地将单元区域用作互连区域。 在另一种形式中，提供了可以通过金属化处理选择性地定义为ROM或RAM的半导体存储器件。