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Patent Agency Ranking
公开(公告)号：US10748818B2
公开(公告)日：2020-08-18
申请号：US16231243
申请日：2018-12-21
Applicant: Texas Instruments Incorporated
Inventor： Tathagata Chatterjee , Steven Loveless , James Robert Todd , Andrew Strachan
IPC: H01L49/02 , H01L21/8234 , H01L21/762 , H01L23/528 , H01L23/00 , H01L23/532
Abstract: In various examples, a method and apparatus are provided to achieve dynamic biasing to mitigate electrical stress. Described examples include a device includes a first resistor portion having a first terminal and a second terminal, and a second resistor portion having a third terminal and a fourth terminal. The device also includes a well in a substrate proximate to the first resistor portion and the second resistor portion and an insulating layer between the well and the first resistor portion and the second resistor portion. The device also includes a transistor having a control terminal coupled to the second terminal of the first resistor portion and the third terminal of the second resistor portion, the transistor having a first current-handling terminal coupled to a first voltage and a second current-handling terminal coupled to a current source and to the well.
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公开(公告)号：US20200013528A1
公开(公告)日：2020-01-09
申请号：US16576809
申请日：2019-09-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Gregory Keith Cestra , Andrew Strachan
Abstract: Methods and apparatus providing a vertically constructed, temperature sensing resistor are disclosed. An example apparatus includes a semiconductor substrate including a plurality of resistor unit cells arranged in an array, each resistor unit cell formed within the semiconductor substrate and including a top contact. A conductive layer located over the semiconductor substrate electrically connects to a subset of the top contacts.
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公开(公告)号：US10431357B2
公开(公告)日：2019-10-01
申请号：US15811069
申请日：2017-11-13
Applicant: Texas Instruments Incorporated
Inventor： Gregory Keith Cestra , Andrew Strachan
Abstract: Methods and apparatus providing a vertically constructed, temperature sensing resistor are disclosed. An example apparatus includes a semiconductor substrate including a first doped region, a second doped region, and a third doped region between the first and second doped regions, the third doped region including a temperature sensitive semiconductor material; a first contact coupled to the first doped region; a second contact opposite the first contact coupled to the second doped region; and an isolation trench to circumscribe the third doped region.
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公开(公告)号：US10937574B2
公开(公告)日：2021-03-02
申请号：US16576809
申请日：2019-09-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Gregory Keith Cestra , Andrew Strachan
Abstract: Methods and apparatus providing a vertically constructed, temperature sensing resistor are disclosed. An example apparatus includes a semiconductor substrate including a plurality of resistor unit cells arranged in an array, each resistor unit cell formed within the semiconductor substrate and including a top contact. A conductive layer located over the semiconductor substrate electrically connects to a subset of the top contacts.
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公开(公告)号：US20190148041A1
公开(公告)日：2019-05-16
申请号：US15811069
申请日：2017-11-13
Applicant: Texas Instruments Incorporated
Inventor： Gregory Keith Cestra , Andrew Strachan
CPC classification number: H01C7/008 , G01K7/01 , H01C7/006 , H01C7/06 , H01C13/02 , H01C17/24 , H01C17/242 , H01L28/20
Abstract: Methods and apparatus providing a vertically constructed, temperature sensing resistor are disclosed. An example apparatus includes a semiconductor substrate including a first doped region, a second doped region, and a third doped region between the first and second doped regions, the third doped region including a temperature sensitive semiconductor material; a first contact coupled to the first doped region; a second contact opposite the first contact coupled to the second doped region; and an isolation trench to circumscribe the third doped region.
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