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公开(公告)号：US20190207010A1
公开(公告)日：2019-07-04
申请号：US15859492
申请日：2017-12-30
IPC分类号： H01L29/66 , H01L21/265 , H01L29/167 , H01L21/8238 , H01L29/10 , H01L21/02 , H01L29/45 , H01L21/285 , H01L21/3213 , H01L21/762 , H01L29/417 , H01L29/06 , H01L29/08 , H01L27/092
CPC分类号： H01L29/665 , H01L21/02164 , H01L21/26513 , H01L21/28518 , H01L21/32137 , H01L21/76202 , H01L21/76224 , H01L21/823814 , H01L21/823871 , H01L21/823878 , H01L27/092 , H01L29/0649 , H01L29/0688 , H01L29/0847 , H01L29/1095 , H01L29/167 , H01L29/4175 , H01L29/456
摘要： An integrated circuit having silicide block integrated with CMOS transistors is formed by forming a silicide block layer of primarily silicon dioxide, free of silicon nitride and silicon oxy-nitride, at less than 400° C. prior to annealing the PMOS sources and drains. A spike anneal process concurrently anneals the PMOS sources and drains and densifies the silicide block layer. The NMOS drain junctions are less than 120 nanometers; the NMOS halo regions include boron. The NMOS and PMOS transistors are laterally separated by an STI oxide layer. A wet deglaze process prior to metal silicide formation removes less than 25 percent of the silicide block layer, and exposes sides of the NMOS drains less than 20 percent of the drain junction depth. The metal silicide does not extend down the NMOS drains sides, directly adjacent to the STI oxide layer, more than 20 percent of the drain junction depth.
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2.发明授权Drift region implant self-aligned to field relief oxide with sidewall dielectric 有权漂移区域植入物自对准到具有侧壁电介质的场释放氧化物公开(公告)号：US09583612B1
公开(公告)日：2017-02-28
申请号：US15003776
申请日：2016-01-21
IPC分类号： H01L29/40 , H01L29/78 , H01L29/66 , H01L21/225 , H01L21/306 , H01L21/308
CPC分类号： H01L29/402 , H01L21/02238 , H01L21/02255 , H01L21/26513 , H01L21/266 , H01L21/32 , H01L21/324 , H01L21/76202 , H01L21/76224 , H01L21/823418 , H01L21/823462 , H01L27/0617 , H01L27/088 , H01L29/063 , H01L29/0653 , H01L29/0847 , H01L29/1083 , H01L29/1095 , H01L29/167 , H01L29/408 , H01L29/42368 , H01L29/66659 , H01L29/7816 , H01L29/7823 , H01L29/7835
摘要： An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region. Dopants are implanted into the substrate under the first opening. Subsequently, dielectric sidewalls are formed along a lateral boundary of the first opening. A field relief oxide is formed by thermal oxidation in the area of the first opening exposed by the dielectric sidewalls. The implanted dopants are diffused into the substrate to form the drift region, extending laterally past the layer of field relief oxide. The dielectric sidewalls and layer of oxide mask are removed after the layer of field relief oxide is formed. A gate is formed over a body of the field-plated FET and over the adjacent drift region. A field plate is formed immediately over the field relief oxide adjacent to the gate.
摘要翻译： 包括场致电FET的集成电路通过在氧化物掩模层中形成第一开口而形成，暴露漂移区域的区域。 在第一开口下将掺杂剂注入到基底中。 随后，沿着第一开口的横向边界形成电介质侧壁。 通过在由电介质侧壁暴露的第一开口的区域中的热氧化形成磁场消除氧化物。 注入的掺杂剂扩散到衬底中以形成漂移区域，横向延伸穿过氧化膜层。 在形成磁场释放氧化物层之后，去除电介质侧壁和氧化物掩模层。 栅极形成在场放电的FET的主体上并在相邻漂移区上方。 在与栅极相邻的磁场浮雕氧化物的正上方形成有场板。
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公开(公告)号：US09698246B1
公开(公告)日：2017-07-04
申请号：US15257243
申请日：2016-09-06
IPC分类号： H01L29/66 , H01L27/092 , H01L29/78 , H01L29/10 , H01L29/167 , H01L29/06 , H01L21/225 , H01L21/265 , H01L29/423
CPC分类号： H01L29/66681 , H01L21/2253 , H01L21/26513 , H01L21/26586 , H01L21/823892 , H01L27/0928 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/1045 , H01L29/1087 , H01L29/1095 , H01L29/167 , H01L29/36 , H01L29/42368 , H01L29/4238 , H01L29/66659 , H01L29/7818 , H01L29/7835
摘要： A laterally diffused MOS (LDMOS) device includes a substrate having a p-epi layer thereon. A p-body region is in the p-epi layer. An ndrift (NDRIFT) region is within the p-body region providing a drain extension region, and a gate dielectric layer is formed over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region, and a patterned gate electrode on the gate dielectric. A DWELL region is within the p-body region, sidewall spacers are on sidewalls of the gate electrode, a source region is within the DWELL region, and a drain region is within the NDRIFT region. The p-body region includes a portion being at least one 0.5 μm wide that has a net p-type doping level above a doping level of the p-epi layer and a net p-type doping profile gradient of at least 5/μm.
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公开(公告)号：US09461046B1
公开(公告)日：2016-10-04
申请号：US14974951
申请日：2015-12-18
IPC分类号： H01L29/66 , H01L27/092 , H01L29/78 , H01L29/06 , H01L21/8238
CPC分类号： H01L29/66681 , H01L21/2253 , H01L21/26513 , H01L21/26586 , H01L21/823892 , H01L27/0928 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/1045 , H01L29/1087 , H01L29/1095 , H01L29/167 , H01L29/36 , H01L29/42368 , H01L29/4238 , H01L29/66659 , H01L29/7818 , H01L29/7835
摘要： A laterally diffused MOS (LDMOS) device includes a substrate having a p-epi layer thereon. A p-body region is in the p-epi layer. An ndrift (NDRIFT) region is within the p-body region providing a drain extension region, and a gate dielectric layer is formed over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region, and a patterned gate electrode on the gate dielectric. A DWELL region is within the p-body region, sidewall spacers are on sidewalls of the gate electrode, a source region is within the DWELL region, and a drain region is within the NDRIFT region. The p-body region includes a portion being at least one 0.5 μm wide that has a net p-type doping level above a doping level of the p-epi layer and a net p-type doping profile gradient of at least 5/μm.
摘要翻译： 横向扩散的MOS（LDMOS）器件包括其上具有p-epi层的衬底。 p体区位于p-epi层。 NDRIFT区域在提供漏极延伸区域的p体区域内部，并且栅极电介质层形成在与NDRIFT区域的结的相邻侧和相对侧的p体区域的沟道区域上方， 以及栅极电介质上的图案化栅电极。 DWELL区域在p体区域内，侧壁间隔物位于栅电极的侧壁上，源区域在DWELL区域内，漏区在NDRIFT区域内。 p体区域包括至少0.5μm宽的部分，其具有高于p-epi层的掺杂水平的净p型掺杂水平和至少5微米的净p型掺杂分布梯度。
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公开(公告)号：US11257814B2
公开(公告)日：2022-02-22
申请号：US16428682
申请日：2019-05-31
摘要： An integrated circuit comprises a semiconductor substrate having a surface. A lateral resistor is arranged in a first plane parallel to the surface of the substrate. A vertical reference resistor comprises a layer arranged in a second plane parallel to the surface of the substrate and deeper than the first plane. This layer is doped to promote current flow in the second plane. The vertical reference resistor further comprises a first trench and a second trench coupled between the layer and the surface of the substrate. The first and second trenches are arranged in a vertical direction orthogonal to the first and the second planes and are doped to impede current flow in the vertical direction. A cross-section of the first and second trenches is two-fold rotationally symmetric around the vertical direction, and the lateral resistor and the first and second trenches have the same temperature coefficient.
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公开(公告)号：US20200013890A1
公开(公告)日：2020-01-09
申请号：US16574394
申请日：2019-09-18
IPC分类号： H01L29/78 , H01L29/08 , H01L29/423 , H01L29/66 , H01L29/10
摘要： Described examples include integrated circuits, drain extended transistors and fabrication methods therefor, including a multi-fingered transistor structure formed in an active region of a semiconductor substrate, in which a transistor drain finger is centered in a multi-finger transistor structure, a transistor body region laterally surrounds the transistor, an outer drift region laterally surrounds an active region of the semiconductor substrate, and one or more inactive or dummy structures are formed at lateral ends of the transistor finger structures.
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公开(公告)号：US20200006550A1
公开(公告)日：2020-01-02
申请号：US16021647
申请日：2018-06-28
IPC分类号： H01L29/78 , H01L29/06 , H01L21/762 , H01L29/66 , H01L21/285 , H01L29/417
摘要： Described examples include integrated circuits, drain extended transistors and fabrication methods in which a silicide block material or other protection layer is formed on a field oxide structure above a drift region to protect the field oxide structure from damage during deglaze processing. Further described examples include a shallow trench isolation (STI) structure that laterally surrounds an active region of a semiconductor substrate, where the STI structure is laterally spaced from the oxide structure, and is formed under gate contacts of the transistor.
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公开(公告)号：US20200006549A1
公开(公告)日：2020-01-02
申请号：US16021601
申请日：2018-06-28
发明人： Alexei Sadovnikov , Andrew Derek Strachan , Henry Litzmann Edwards , Dhanoop Varghese , Xiaoju Wu , Binghua Hu , James Robert Todd
IPC分类号： H01L29/78 , H01L29/66 , H01L29/10 , H01L29/08 , H01L21/266 , H01L21/265
摘要： Described examples include integrated circuits, drain extended transistors and fabrication methods in which an oxide structure is formed over a drift region of a semiconductor substrate, and a shallow implantation process is performed using a first mask that exposes the oxide structure and a first portion of the semiconductor substrate to form a first drift region portion for connection to a body implant region. A second drift region portion is implanted in the semiconductor substrate under the oxide structure by a second implantation process using the first mask at a higher implant energy.
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公开(公告)号：US09887288B2
公开(公告)日：2018-02-06
申请号：US14957223
申请日：2015-12-02
IPC分类号： H01L21/336 , H01L29/78 , H01L29/66 , H01L29/10 , H01L29/06 , H01L29/08 , H01L29/167 , H01L21/265 , H01L21/324
CPC分类号： H01L29/7816 , H01L21/26513 , H01L21/324 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/086 , H01L29/0878 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/167 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： A laterally diffused metal oxide semiconductor (LDMOS) device includes a substrate having a p-epi layer thereon, a p-body region in the p-epi layer and an ndrift (NDRIFT) region within the p-body to provide a drain extension region. A gate stack includes a gate dielectric layer over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region. A patterned gate electrode is on the gate dielectric. A DWELL region is within the p-body region. A source region is within the DWELL region, and a drain region is within the NDRIFT region. An effective channel length (Leff) for the LDMOS device is 75 nm to 150 nm which evidences a DWELL implant that utilized an edge of the gate electrode to delineate an edge of a DWELL ion implant so that the DWELL region is self-aligned to the gate electrode.
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公开(公告)号：US11374124B2
公开(公告)日：2022-06-28
申请号：US16021647
申请日：2018-06-28
IPC分类号： H01L29/78 , H01L29/06 , H01L21/762 , H01L21/285 , H01L29/417 , H01L29/66 , H01L49/02 , H01L27/06
摘要： Described examples include integrated circuits, drain extended transistors and fabrication methods in which a silicide block material or other protection layer is formed on a field oxide structure above a drift region to protect the field oxide structure from damage during deglaze processing. Further described examples include a shallow trench isolation (STI) structure that laterally surrounds an active region of a semiconductor substrate, where the STI structure is laterally spaced from the oxide structure, and is formed under gate contacts of the transistor.
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