公开(公告)号：US20240071539A1

公开(公告)日：2024-02-29

申请号：US18114449

申请日：2023-02-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Likhita Chandrashekara ,  Yash Didhe ,  Rajat Chauhan ,  Devraj Rajagopal

IPC: G11C17/18 ,  G11C17/16 ,  H01L23/525 ,  H10B20/25

CPC classification number: G11C17/18 ,  G11C17/16 ,  H01L23/5256 ,  H10B20/25

Abstract: One example includes an integrated circuit with a sense amplifier that includes a first inverter having a first positive power terminal, a first input and a first output; and a second inverter having a second positive power terminal, a second input connected to the first output and a second output connected to the first input. The integrated circuit also includes a reference resistor connected between a positive voltage rail and the second positive power terminal. A fuse is connected between the positive voltage rail and the first positive power terminal.

公开(公告)号：US20210119620A1

公开(公告)日：2021-04-22

申请号：US16930861

申请日：2020-07-16

Applicant: Texas Instruments Incorporated

Inventor： Pranshu Kalra ,  Srikanth Srinivasan ,  Devraj Rajagopal

IPC: H03K5/01 ,  H03K17/687 ,  H03K19/20

Abstract: A receiver includes a low-side buffer having an input terminal coupled to receive an input signal and having an output terminal coupled to a buffer terminal. Responsive to the input signal being LOW, the low-side buffer is configured to couple the buffer terminal to ground. The receiver also includes a high-side buffer having an input terminal coupled to receive the input signal and having an output terminal coupled to the buffer terminal. Responsive to the input signal being HIGH, the high-side buffer is configured to provide an I/O voltage at the buffer terminal. The receiver also includes an output stage coupled to the buffer terminal and having a low voltage terminal configured to receive a low supply voltage. The output stage is configured to provide an output signal responsive to the I/O voltage at the buffer terminal, wherein the output signal is lower than the I/O voltage.

公开(公告)号：US11063580B2

公开(公告)日：2021-07-13

申请号：US16930861

申请日：2020-07-16

Applicant: Texas Instruments Incorporated

Inventor： Pranshu Kalra ,  Srikanth Srinivasan ,  Devraj Rajagopal

IPC: H03K17/687 ,  H03K5/01 ,  H03K19/20 ,  H03K19/0175 ,  H03K19/0185 ,  H03K17/06

Abstract: A receiver includes a low-side buffer having an input terminal coupled to receive an input signal and having an output terminal coupled to a buffer terminal. Responsive to the input signal being LOW, the low-side buffer is configured to couple the buffer terminal to ground. The receiver also includes a high-side buffer having an input terminal coupled to receive the input signal and having an output terminal coupled to the buffer terminal. Responsive to the input signal being HIGH, the high-side buffer is configured to provide an I/O voltage at the buffer terminal. The receiver also includes an output stage coupled to the buffer terminal and having a low voltage terminal configured to receive a low supply voltage. The output stage is configured to provide an output signal responsive to the I/O voltage at the buffer terminal, wherein the output signal is lower than the I/O voltage.

公开(公告)号：US20230397413A1

公开(公告)日：2023-12-07

申请号：US17876834

申请日：2022-07-29

Applicant: Texas Instruments Incorporated

Inventor： Krishnanunni B ,  Devraj Rajagopal

IPC: H01L27/112

CPC classification number: H01L27/11286

Abstract: A semiconductor device includes core circuits configured to operate at a core bias potential, input/output (I/O) circuits configured to operate at an I/O bias potential higher than the core bias potential, and a non-volatile memory having a peripheral circuit configured to operate at a memory program bias potential that is higher than the I/O bias potential. The peripheral circuit is also configured to operate at the core bias potential. The peripheral circuit has an input buffer; a threshold potential at an input buffer input node of the input buffer is less than the core bias potential. The peripheral circuit may be manifested as a low voltage supply detection circuit. The peripheral circuit may be manifested as a level shifter circuit. The peripheral circuit may be manifested as a sense circuit. The input buffer may include a drain extended core transistor to provide the desired threshold potential.

公开(公告)号：US10666257B1

公开(公告)日：2020-05-26

申请号：US16502198

申请日：2019-07-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srikanth Srinivasan ,  Devraj Rajagopal

IPC: H03K19/007 ,  H03K19/0185

Abstract: A wide-voltage range, failsafe output interface module including a low-voltage, drain extended MOSFETs has been proposed to prevent the flow of reverse current during a failsafe operation while ensuring the MOSFETs are not subject to voltage over their voltage tolerance levels, improving reliability of an output interface module without resorting to more costly transistors with thicker films.