公开(公告)号：US10249504B2

公开(公告)日：2019-04-02

申请号：US15864802

申请日：2018-01-08

Applicant: Texas Instruments Incorporated

Inventor： Jian Jun Kong ,  She Yu Tang ,  Tian Yi Zhang ,  Qin Xu Yu ,  Sheng Pin Yang

IPC: H01L21/304 ,  H01L21/311 ,  H01L21/683 ,  H01L21/3213

Abstract: In some embodiments, a method includes wet-etching a first film layer of a plurality of film layers stacked on a semiconductor substrate, the wet-etching of the first film layer performed using a first chemical, where the first film layer is an outermost film layer stacked on the semiconductor substrate. The method further includes wet-etching a second film layer of the plurality of film layers using a second chemical. The method also includes using a mechanical grinding wheel to grind the semiconductor substrate to reduce a thickness of the semiconductor substrate.

公开(公告)号：US20240429290A1

公开(公告)日：2024-12-26

申请号：US18751877

申请日：2024-06-24

Applicant: Texas Instruments Incorporated

Inventor： Ya Ping Chen ,  Yunlong Liu ,  Hong Yang ,  Jing Hu ,  Chao Zhuang ,  Peng Li ,  Sheng Pin Yang

IPC: H01L29/40 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device includes etching a first trench and a second trench in an epitaxial layer over a semiconductor and forming a dielectric liner within the trenches. A photoresist layer is formed within the trenches and over the epitaxial layer and given a post-exposure bake at a first temperature. The photoresist layer is then given an adhesion-promoting bake at a greater second temperature; The photoresist layer is then removed from a top portion the trenches, thereby exposing a top portion of the dielectric liner and leaving a remaining portion of the photoresist in a bottom portion of the trenches. The exposed dielectric liner is etched, thereby leaving a remaining portion of the dielectric liner in the top portion of the trenches. The remaining portion of the photoresist is removed and the trenches are filled with a polysilicon layer.

公开(公告)号：US20190067017A1

公开(公告)日：2019-02-28

申请号：US15864802

申请日：2018-01-08

Applicant: Texas Instruments Incorporated

Inventor： Jian Jun Kong ,  She Yu Tang ,  Tian Yi Zhang ,  Qin Xu Yu ,  Sheng Pin Yang

IPC: H01L21/304 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/683

Abstract: In some embodiments, a method includes wet-etching a first film layer of a plurality of film layers stacked on a semiconductor substrate, the wet-etching of the first film layer performed using a first chemical, where the first film layer is an outermost film layer stacked on the semiconductor substrate. The method further includes wet-etching a second film layer of the plurality of film layers using a second chemical. The method also includes using a mechanical grinding wheel to grind the semiconductor substrate to reduce a thickness of the semiconductor substrate.

公开(公告)号：US20240361699A1

公开(公告)日：2024-10-31

申请号：US18308901

申请日：2023-04-28

Applicant: Texas Instruments Incorporated

Inventor： Yunlong Liu ,  Hong Yang ,  Peng Li ,  Yung Shan Chang ,  Sheng Pin Yang ,  Ya Ping Chen

IPC: G03F7/22 ,  G01B5/06 ,  G01B11/06

CPC classification number: G03F7/22 ,  G01B5/06 ,  G01B11/06 ,  G03F7/039

Abstract: A method of forming a microelectronic device includes forming positive tone photoresist on the microelectronic device, filling a trench, extending over a top surface adjacent to the trench, and covering a thickness monitor on a substrate containing the microelectronic device. The photoresist in and over the trench is exposed at a trench energy dose, and the photoresist in the monitor area is exposed at a monitor energy dose that is less than the trench energy dose. The photoresist is developed, leaving photoresist in the trench having an in-trench thickness less than the depth of the trench and leaving an in-monitor thickness of the photoresist on the monitor area less than an unexposed thickness. The in-monitor thickness of the photoresist on the monitor area may be measured and the measured thickness value may be used with a calibration chart to estimate the in-trench thickness of the photoresist.

公开(公告)号：US10566204B2

公开(公告)日：2020-02-18

申请号：US16282344

申请日：2019-02-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jian Jun Kong ,  She Yu Tang ,  Tian Yi Zhang ,  Qin Xu Yu ,  Sheng Pin Yang

IPC: H01L21/304 ,  H01L21/311 ,  H01L21/683 ,  H01L21/3213

Abstract: In some embodiments, a method of forming an integrated circuit includes providing a semiconductor substrate having an electronic circuit formed on a front side, and having a first material layer located over a second side of the substrate and a second material layer located between the first material layer and the second side. At least a portion of the first material layer is removed using a first chemical etching process, thereby exposing the second material layer. At least a portion of the second material layer is removed using a second chemical etching process. A portion of the substrate is then mechanically removed from the second side.