公开(公告)号：US20110284950A1

公开(公告)日：2011-11-24

申请号：US12800662

申请日：2010-05-20

申请人： Timothy D. Henson ,  Ling Ma ,  Hugo Burke ,  David P. Jones ,  Kapil Kelkar ,  Niraj Ranjan

发明人： Timothy D. Henson ,  Ling Ma ,  Hugo Burke ,  David P. Jones ,  Kapil Kelkar ,  Niraj Ranjan

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/265 ,  H01L21/30625 ,  H01L29/0878 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66734

摘要： Disclosed is a method for fabricating a shallow and narrow trench field-effect transistor (trench FET). The method includes forming a trench within a semiconductor substrate of a first conductivity type, the trench including sidewalls and a bottom portion. The method further includes forming a substantially uniform gate dielectric in the trench, and forming a gate electrode within said trench and over said gate dielectric. The method also includes doping the semiconductor substrate to form a channel region of a second conductivity type after forming the trench. In one embodiment, the doping step is performed after forming the gate dielectric and after forming the gate electrode. In another embodiment, the doping step is performed after forming the gate dielectric, but prior to forming the gate electrode. Structures formed by the invention's method are also disclosed.

摘要翻译： 公开了一种制造浅沟槽场效应晶体管（沟槽FET）的方法。 该方法包括在第一导电类型的半导体衬底内形成沟槽，沟槽包括侧壁和底部。 该方法还包括在沟槽中形成基本上均匀的栅极电介质，以及在所述沟槽内和所述栅极电介质上方形成栅电极。 该方法还包括在形成沟槽之后掺杂半导体衬底以形成第二导电类型的沟道区。 在一个实施例中，在形成栅极电介质之后并在形成栅电极之后执行掺杂步骤。 在另一个实施例中，掺杂步骤在形成栅极电介质之后，但在形成栅电极之前进行。 还公开了通过本发明方法形成的结构。

公开(公告)号：US09653597B2

公开(公告)日：2017-05-16

申请号：US12800662

申请日：2010-05-20

申请人： Timothy D. Henson ,  Ling Ma ,  Hugo Burke ,  David P. Jones ,  Kapil Kelkar ,  Niraj Ranjan ,  Igor Bol

发明人： Timothy D. Henson ,  Ling Ma ,  Hugo Burke ,  David P. Jones ,  Kapil Kelkar ,  Niraj Ranjan ,  Igor Bol

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/265 ,  H01L21/30625 ,  H01L29/0878 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66734

摘要： Disclosed is a method for fabricating a shallow and narrow trench field-effect transistor (trench FET). The method includes forming a trench within a semiconductor substrate of a first conductivity type, the trench including sidewalls and a bottom portion. The method further includes forming a substantially uniform gate dielectric in the trench, and forming a gate electrode within said trench and over said gate dielectric. The method also includes doping the semiconductor substrate to form a channel region of a second conductivity type after forming the trench. In one embodiment, the doping step is performed after forming the gate dielectric and after forming the gate electrode. In another embodiment, the doping step is performed after forming the gate dielectric, but prior to forming the gate electrode. Structures formed by the invention's method are also disclosed.