公开(公告)号：US20100146201A1

公开(公告)日：2010-06-10

申请号：US12612215

申请日：2009-11-04

申请人： Tomohiro Kawakubo ,  Syusaku Yamaguchi ,  Hitoshi Ikeda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Tatsuya Kanda ,  Yoshinobu Yamamoto ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

发明人： Tomohiro Kawakubo ,  Syusaku Yamaguchi ,  Hitoshi Ikeda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Tatsuya Kanda ,  Yoshinobu Yamamoto ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

IPC分类号： G06F12/00

CPC分类号： G11C11/406 ,  G11C7/1027 ,  G11C8/12 ,  G11C11/40618 ,  G11C11/4087

摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.

公开(公告)号：US20080151670A1

公开(公告)日：2008-06-26

申请号：US11709867

申请日：2007-02-23

申请人： Tomohiro Kawakubo ,  Syusaku Yamaguchi ,  Hitoshi Ikeda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Tatsuya Kanda ,  Yoshinobu Yamamoto ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

发明人： Tomohiro Kawakubo ,  Syusaku Yamaguchi ,  Hitoshi Ikeda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Tatsuya Kanda ,  Yoshinobu Yamamoto ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C7/1027 ,  G11C8/12 ,  G11C11/40618 ,  G11C11/4087

摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.

摘要翻译： 提供了一种存储装置，其中已经解决了由存储装置的刷新操作引起的有效带宽的减少，存储装置的存储器控​​制器及其存储器系统。 响应于来自存储器控制器的命令操作的存储器件具有分别具有存储器核心的多个存储体，包括存储器单元阵列和解码器，并且由存储体地址选择; 以及控制电路，其响应于后台刷新命令使由所述存储器控制器设置的刷新对象组内的存储器核心依次执行对应于由所述存储器控制器设置的刷新突发长度的次数的刷新操作， 并且响应于正常操作命令，在由存储器核心执行的刷新操作期间进一步使存储器内的存储器核心在刷新对象组之外并由存储体地址选择以执行与正常操作命令相对应的正常存储器操作 在刷新目标银行。

公开(公告)号：US08077537B2

公开(公告)日：2011-12-13

申请号：US12612215

申请日：2009-11-04

申请人： Tomohiro Kawakubo ,  Syusaku Yamaguchi ,  Hitoshi Ikeda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Tatsuya Kanda ,  Yoshinobu Yamamoto ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

发明人： Tomohiro Kawakubo ,  Syusaku Yamaguchi ,  Hitoshi Ikeda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Tatsuya Kanda ,  Yoshinobu Yamamoto ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C7/1027 ,  G11C8/12 ,  G11C11/40618 ,  G11C11/4087

摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.

摘要翻译： 提供了一种存储装置，其中已经解决了由存储装置的刷新操作引起的有效带宽的减少，存储装置的存储器控​​制器及其存储器系统。 响应于来自存储器控制器的命令操作的存储器件具有分别具有存储器核心的多个存储体，包括存储器单元阵列和解码器，并且由存储体地址选择; 以及控制电路，其响应于后台刷新命令使由所述存储器控制器设置的刷新对象组内的存储器核心依次执行对应于由所述存储器控制器设置的刷新突发长度的次数的刷新操作， 并且响应于正常操作命令，在由存储器核心执行的刷新操作期间进一步使存储器内的存储器核心在刷新对象组之外并由存储体地址选择以执行与正常操作命令相对应的正常存储器操作 在刷新目标银行。

公开(公告)号：US08004921B2

公开(公告)日：2011-08-23

申请号：US12612247

申请日：2009-11-04

申请人： Tomohiro Kawakubo ,  Syusaku Yamaguchi ,  Hitoshi Ikeda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Tatsuya Kanda ,  Yoshinobu Yamamoto ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

发明人： Tomohiro Kawakubo ,  Syusaku Yamaguchi ,  Hitoshi Ikeda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Tatsuya Kanda ,  Yoshinobu Yamamoto ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C7/1027 ,  G11C8/12 ,  G11C11/40618 ,  G11C11/4087

摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.

公开(公告)号：US20100172200A1

公开(公告)日：2010-07-08

申请号：US12612247

申请日：2009-11-04

申请人： Tomohiro KAWAKUBO ,  Syusaku Yamaguchi ,  Hitoshi Ikeda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Tatsuya Kanda ,  Yoshinobu Yamamoto ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

发明人： Tomohiro KAWAKUBO ,  Syusaku Yamaguchi ,  Hitoshi Ikeda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Tatsuya Kanda ,  Yoshinobu Yamamoto ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C11/406 ,  G11C7/1027 ,  G11C8/12 ,  G11C11/40618 ,  G11C11/4087

摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.

摘要翻译： 提供了一种存储装置，其中已经解决了由存储装置的刷新操作引起的有效带宽的减少，存储装置的存储器控​​制器及其存储器系统。 响应于来自存储器控制器的命令操作的存储器件具有分别具有存储器核心的多个存储体，包括存储器单元阵列和解码器，并且由存储体地址选择; 以及控制电路，其响应于后台刷新命令使由所述存储器控制器设置的刷新对象组内的存储器核心依次执行对应于由所述存储器控制器设置的刷新突发长度的次数的刷新操作， 并且响应于正常操作命令，在由存储器核心执行的刷新操作期间进一步使存储器内的存储器核心在刷新对象组之外并由存储体地址选择以执行与正常操作命令相对应的正常存储器操作 在刷新目标银行。

公开(公告)号：US07729200B2

公开(公告)日：2010-06-01

申请号：US12000840

申请日：2007-12-18

申请人： Hitoshi Ikeda ,  Takahiko Sato ,  Tatsuya Kanda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

发明人： Hitoshi Ikeda ,  Takahiko Sato ,  Tatsuya Kanda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

IPC分类号： G11C7/10

CPC分类号： G11C8/12 ,  G06F12/0207

摘要： The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

公开(公告)号：US20080189467A1

公开(公告)日：2008-08-07

申请号：US12000840

申请日：2007-12-18

申请人： Hitoshi Ikeda ,  Takahiko Sato ,  Tatsuya Kanda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

发明人： Hitoshi Ikeda ,  Takahiko Sato ,  Tatsuya Kanda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

IPC分类号： G06F12/00

CPC分类号： G11C8/12 ,  G06F12/0207

摘要： The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

公开(公告)号：US07668040B2

公开(公告)日：2010-02-23

申请号：US11707252

申请日：2007-02-16

申请人： Hitoshi Ikeda ,  Takahiko Sato ,  Tatsuya Kanda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

发明人： Hitoshi Ikeda ,  Takahiko Sato ,  Tatsuya Kanda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

IPC分类号： G11C7/10

CPC分类号： G11C8/12 ,  G06F12/0207

摘要： The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

摘要翻译： 存储器件具有：多个存储体，每个存储体具有存储单元阵列，该存储单元阵列具有分别由行地址选择的多个页面区域，并且每个区域由银行地址选择; 行控制器，其响应于第一操作码来控制每个存储体内的页面区域的激活; 和一组数据输入/输出端子。 基于列地址访问每个激活的页面区域内的存储单元区域。 行控制器响应于与第一命令一起提供的多存储体信息数据和提供的库地址，为多个存储体生成存储体激活信号，并且响应于第一指令生成多个存储体的行地址 提供的银行地址和提供的行地址。 响应于行激活信号和由行地址计算器生成的行地址，多个存储体激活页面区域。

公开(公告)号：US20080151678A1

公开(公告)日：2008-06-26

申请号：US11707252

申请日：2007-02-16

申请人： Hitoshi Ikeda ,  Takahiko Sato ,  Tatsuya Kanda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

发明人： Hitoshi Ikeda ,  Takahiko Sato ,  Tatsuya Kanda ,  Toshiya Uchida ,  Hiroyuki Kobayashi ,  Satoru Shirakawa ,  Tetsuo Miyamoto ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

IPC分类号： G11C8/12

CPC分类号： G11C8/12 ,  G06F12/0207

摘要： The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

摘要翻译： 存储器件具有：多个存储体，每个存储体具有分别由行地址选择的多个页面区域的存储单元阵列，并且每个存储单元阵列由存储体地址选择; 行控制器，其响应于第一操作码来控制每个存储体内的页面区域的激活; 和一组数据输入/输出端子。 基于列地址访问每个激活的页面区域内的存储单元区域。 行控制器响应于与第一命令一起提供的多存储体信息数据和提供的库地址，为多个存储体生成存储体激活信号，并且响应于第一指令生成多个存储体的行地址 提供的银行地址和提供的行地址。 响应于行激活信号和由行地址计算器生成的行地址，多个存储体激活页面区域。

公开(公告)号：US20080151677A1

公开(公告)日：2008-06-26

申请号：US11698286

申请日：2007-01-26

申请人： Takahiko Sato ,  Toshiya Uchida ,  Tatsuya Kanda ,  Tetsuo Miyamoto ,  Satoru Shirakawa ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

发明人： Takahiko Sato ,  Toshiya Uchida ,  Tatsuya Kanda ,  Tetsuo Miyamoto ,  Satoru Shirakawa ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

IPC分类号： G11C8/12

CPC分类号： G11C11/4087 ,  G09G5/393 ,  G09G5/395 ,  G11C8/12

摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.

摘要翻译： 提供能够有效地访问二维排列数据的矩形区域的图像存储器，图像存储器系统和存储器控制器。 存储装置具有：具有多个存储单元区域的存储单元阵列，每个存储单元区域由地址选择; 多个输入/输出端子; 以及设置在存储单元阵列和多个输入/输出端子之间的输入/输出单元。 每个存储单元区域分别存储与多个输入/输出端子相对应的多个字节或位的数据，并且存储单元阵列和输入/输出单元访问存储在第一存储器中的多个字节或位 基于与第一操作码相对应的字节或比特的输入地址和组合信息，与第一存储器单元相邻的第二存储器单元区域中的对应于输入地址的单位区域和与第一存储器单元相邻的第二存储单元区域中， 在所访问的第一和第二存储器单元区域内的字节或比特，基于组合信息将多个字节或比特的组合与多个输入/输出终端相关联。