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公开(公告)号：US07668040B2
公开(公告)日：2010-02-23
申请号：US11707252
申请日：2007-02-16
申请人： Hitoshi Ikeda , Takahiko Sato , Tatsuya Kanda , Toshiya Uchida , Hiroyuki Kobayashi , Satoru Shirakawa , Tetsuo Miyamoto , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Hitoshi Ikeda , Takahiko Sato , Tatsuya Kanda , Toshiya Uchida , Hiroyuki Kobayashi , Satoru Shirakawa , Tetsuo Miyamoto , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C7/10
CPC分类号： G11C8/12 , G06F12/0207
摘要： The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.
摘要翻译： 存储器件具有：多个存储体，每个存储体具有存储单元阵列，该存储单元阵列具有分别由行地址选择的多个页面区域，并且每个区域由银行地址选择; 行控制器，其响应于第一操作码来控制每个存储体内的页面区域的激活; 和一组数据输入/输出端子。 基于列地址访问每个激活的页面区域内的存储单元区域。 行控制器响应于与第一命令一起提供的多存储体信息数据和提供的库地址，为多个存储体生成存储体激活信号，并且响应于第一指令生成多个存储体的行地址 提供的银行地址和提供的行地址。 响应于行激活信号和由行地址计算器生成的行地址，多个存储体激活页面区域。
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公开(公告)号：US20080151678A1
公开(公告)日：2008-06-26
申请号：US11707252
申请日：2007-02-16
申请人： Hitoshi Ikeda , Takahiko Sato , Tatsuya Kanda , Toshiya Uchida , Hiroyuki Kobayashi , Satoru Shirakawa , Tetsuo Miyamoto , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Hitoshi Ikeda , Takahiko Sato , Tatsuya Kanda , Toshiya Uchida , Hiroyuki Kobayashi , Satoru Shirakawa , Tetsuo Miyamoto , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C8/12
CPC分类号： G11C8/12 , G06F12/0207
摘要： The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.
摘要翻译： 存储器件具有：多个存储体，每个存储体具有分别由行地址选择的多个页面区域的存储单元阵列，并且每个存储单元阵列由存储体地址选择; 行控制器，其响应于第一操作码来控制每个存储体内的页面区域的激活; 和一组数据输入/输出端子。 基于列地址访问每个激活的页面区域内的存储单元区域。 行控制器响应于与第一命令一起提供的多存储体信息数据和提供的库地址，为多个存储体生成存储体激活信号，并且响应于第一指令生成多个存储体的行地址 提供的银行地址和提供的行地址。 响应于行激活信号和由行地址计算器生成的行地址，多个存储体激活页面区域。
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公开(公告)号：US07729200B2
公开(公告)日：2010-06-01
申请号：US12000840
申请日：2007-12-18
申请人： Hitoshi Ikeda , Takahiko Sato , Tatsuya Kanda , Toshiya Uchida , Hiroyuki Kobayashi , Satoru Shirakawa , Tetsuo Miyamoto , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Hitoshi Ikeda , Takahiko Sato , Tatsuya Kanda , Toshiya Uchida , Hiroyuki Kobayashi , Satoru Shirakawa , Tetsuo Miyamoto , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C7/10
CPC分类号： G11C8/12 , G06F12/0207
摘要： The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.
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公开(公告)号：US20080189467A1
公开(公告)日：2008-08-07
申请号：US12000840
申请日：2007-12-18
申请人： Hitoshi Ikeda , Takahiko Sato , Tatsuya Kanda , Toshiya Uchida , Hiroyuki Kobayashi , Satoru Shirakawa , Tetsuo Miyamoto , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Hitoshi Ikeda , Takahiko Sato , Tatsuya Kanda , Toshiya Uchida , Hiroyuki Kobayashi , Satoru Shirakawa , Tetsuo Miyamoto , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G06F12/00
CPC分类号： G11C8/12 , G06F12/0207
摘要： The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.
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公开(公告)号：US20080151677A1
公开(公告)日：2008-06-26
申请号：US11698286
申请日：2007-01-26
申请人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C8/12
CPC分类号： G11C11/4087 , G09G5/393 , G09G5/395 , G11C8/12
摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.
摘要翻译： 提供能够有效地访问二维排列数据的矩形区域的图像存储器，图像存储器系统和存储器控制器。 存储装置具有：具有多个存储单元区域的存储单元阵列，每个存储单元区域由地址选择; 多个输入/输出端子; 以及设置在存储单元阵列和多个输入/输出端子之间的输入/输出单元。 每个存储单元区域分别存储与多个输入/输出端子相对应的多个字节或位的数据，并且存储单元阵列和输入/输出单元访问存储在第一存储器中的多个字节或位 基于与第一操作码相对应的字节或比特的输入地址和组合信息，与第一存储器单元相邻的第二存储器单元区域中的对应于输入地址的单位区域和与第一存储器单元相邻的第二存储单元区域中， 在所访问的第一和第二存储器单元区域内的字节或比特，基于组合信息将多个字节或比特的组合与多个输入/输出终端相关联。
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公开(公告)号：US08015389B2
公开(公告)日：2011-09-06
申请号：US12000953
申请日：2007-12-19
申请人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G06F12/06
CPC分类号： G11C11/4087 , G09G5/393 , G09G5/395 , G11C8/12
摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.
摘要翻译： 提供能够有效地访问二维排列数据的矩形区域的图像存储器，图像存储器系统和存储器控制器。 存储装置具有：具有多个存储单元区域的存储单元阵列，每个存储单元区域由地址选择; 多个输入/输出端子; 以及设置在存储单元阵列和多个输入/输出端子之间的输入/输出单元。 每个存储单元区域分别存储与多个输入/输出端子相对应的多个字节或位的数据，并且存储单元阵列和输入/输出单元访问存储在第一存储器中的多个字节或位 基于与第一操作码相对应的字节或比特的输入地址和组合信息，与第一存储器单元相邻的第二存储器单元区域中的对应于输入地址的单位区域和与第一存储器单元相邻的第二存储单元区域中， 在所访问的第一和第二存储器单元区域内的字节或比特，基于组合信息将多个字节或比特的组合与多个输入/输出终端相关联。
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公开(公告)号：US07774577B2
公开(公告)日：2010-08-10
申请号：US12000952
申请日：2007-12-19
申请人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
CPC分类号： G11C11/4087 , G09G5/393 , G09G5/395 , G11C8/12
摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.
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公开(公告)号：US20090027988A1
公开(公告)日：2009-01-29
申请号：US12000953
申请日：2007-12-19
申请人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
CPC分类号： G11C11/4087 , G09G5/393 , G09G5/395 , G11C8/12
摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.
摘要翻译： 提供能够有效地访问二维排列数据的矩形区域的图像存储器，图像存储器系统和存储器控制器。 存储装置具有：具有多个存储单元区域的存储单元阵列，每个存储单元区域由地址选择; 多个输入/输出端子; 以及设置在存储单元阵列和多个输入/输出端子之间的输入/输出单元。 每个存储单元区域分别存储与多个输入/输出端子相对应的多个字节或位的数据，并且存储单元阵列和输入/输出单元访问存储在第一存储器中的多个字节或位 基于与第一操作码相对应的字节或比特的输入地址和组合信息，与第一存储器单元相邻的第二存储器单元区域中的对应于输入地址的单位区域和与第一存储器单元相邻的第二存储器单元区域中， 在所访问的第一和第二存储器单元区域内的字节或比特，基于组合信息将多个字节或比特的组合与多个输入/输出终端相关联。
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公开(公告)号：US07814294B2
公开(公告)日：2010-10-12
申请号：US11698286
申请日：2007-01-26
申请人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G06F12/06
CPC分类号： G11C11/4087 , G09G5/393 , G09G5/395 , G11C8/12
摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.
摘要翻译： 提供能够有效地访问二维排列数据的矩形区域的图像存储器，图像存储器系统和存储器控制器。 存储装置具有：具有多个存储单元区域的存储单元阵列，每个存储单元区域由地址选择; 多个输入/输出端子; 以及设置在存储单元阵列和多个输入/输出端子之间的输入/输出单元。 每个存储单元区域分别存储与多个输入/输出端子相对应的多个字节或位的数据，并且存储单元阵列和输入/输出单元访问存储在第一存储器中的多个字节或位 基于与第一操作码相对应的字节或比特的输入地址和组合信息，与第一存储器单元相邻的第二存储器单元区域中的对应于输入地址的单位区域和与第一存储器单元相邻的第二存储单元区域中， 在所访问的第一和第二存储器单元区域内的字节或比特，基于组合信息将多个字节或比特的组合与多个输入/输出终端相关联。
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公开(公告)号：US07114025B2
公开(公告)日：2006-09-26
申请号：US10689486
申请日：2003-10-21
申请人： Tatsuya Kanda , Akihiro Funyu , Takahiko Sato , Yoshiaki Okuyama , Jun Ohno , Hitoshi Ikeda
发明人： Tatsuya Kanda , Akihiro Funyu , Takahiko Sato , Yoshiaki Okuyama , Jun Ohno , Hitoshi Ikeda
CPC分类号： G11C11/406 , G11C11/401 , G11C11/40603 , G11C29/02 , G11C29/028 , G11C29/50 , G11C29/50016
摘要： A semiconductor memory includes a refresh timer and an arbiter for determining the order of precedence between an access operation and a refresh operation, in order to automatically perform refresh operations inside the memory. A detecting circuit operates in a test mode and outputs a detection signal indicating that the refresh operation is yet to be performed, when a new internal refresh request occurs before the refresh operation is performed. For example, the detection signal is output when the interval of access requests is short and no refresh operation can be inserted between the access operations. That is, in the semiconductor memory in which refresh operations are performed automatically, it is possible to evaluate the minimum interval of supplying access requests. As a result, the evaluation time can be reduced with a reduction in the development period of the semiconductor memory.
摘要翻译： 半导体存储器包括刷新定时器和用于确定访问操作和刷新操作之间的优先级顺序的仲裁器，以便自动执行存储器内的刷新操作。 检测电路在测试模式下工作，并且在执行刷新操作之前发生新的内部刷新请求时，输出指示刷新操作尚未执行的检测信号。 例如，当访问请求的间隔短并且在访问操作之间不能插入刷新操作时，输出检测信号。 也就是说，在自动执行刷新操作的半导体存储器中，可以评估提供访问请求的最小间隔。 结果，随着半导体存储器的显影周期的减少，可以减少评估时间。
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