公开(公告)号：US20240429316A1

公开(公告)日：2024-12-26

申请号：US18822485

申请日：2024-09-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jhe Hsu ,  Che-Yi Ho

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/165

Abstract: A semiconductor device includes a gate structure on a substrate and an epitaxial layer adjacent to the gate structure, in which the epitaxial layer includes a first buffer layer, a second buffer layer on the first buffer layer, a bulk layer on the second buffer layer, a first cap layer on the bulk layer, and a second cap layer on the first cap layer. Preferably, the bottom surface of the first buffer layer includes a linear surface, a bottom surface of the second buffer layer includes a curve, and the second buffer layer includes a linear sidewall.

公开(公告)号：US20230231051A1

公开(公告)日：2023-07-20

申请号：US17672733

申请日：2022-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jhe Hsu ,  Che-Yi Ho

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639

Abstract: A semiconductor device includes a gate structure on a substrate and an epitaxial layer adjacent to the gate structure, in which the epitaxial layer includes a first buffer layer, a second buffer layer on the first buffer layer, a bulk layer on the second buffer layer, a first cap layer on the bulk layer, and a second cap layer on the first cap layer. Preferably, the bottom surface of the first buffer layer includes a linear surface, a bottom surface of the second buffer layer includes a curve, and the second buffer layer includes a linear sidewall.

公开(公告)号：US12107164B2

公开(公告)日：2024-10-01

申请号：US17672733

申请日：2022-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jhe Hsu ,  Che-Yi Ho

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0847 ,  H01L29/165

Abstract: A semiconductor device includes a gate structure on a substrate and an epitaxial layer adjacent to the gate structure, in which the epitaxial layer includes a first buffer layer, a second buffer layer on the first buffer layer, a bulk layer on the second buffer layer, a first cap layer on the bulk layer, and a second cap layer on the first cap layer. Preferably, the bottom surface of the first buffer layer includes a linear surface, a bottom surface of the second buffer layer includes a curve, and the second buffer layer includes a linear sidewall.