公开(公告)号：US20240154049A1

公开(公告)日：2024-05-09

申请号：US18411782

申请日：2024-01-12

Applicant: First Solar, Inc.

Inventor： Holly Ann Blaydes ,  Kristian William Andreini ,  William Hullinger Huber ,  Eugene Thomas Hinners ,  Joseph John Shiang ,  Yong Liang ,  Jongwoo Choi

IPC: H01L31/0272 ,  C23C14/06 ,  H01L21/02 ,  H01L31/0224 ,  H01L31/0296 ,  H01L31/0392 ,  H01L31/072 ,  H01L31/073 ,  H01L31/18

CPC classification number: H01L31/0272 ,  C23C14/0629 ,  H01L21/02422 ,  H01L21/02477 ,  H01L21/0248 ,  H01L21/02483 ,  H01L21/02491 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/0256 ,  H01L21/02562 ,  H01L31/022466 ,  H01L31/0296 ,  H01L31/02963 ,  H01L31/02966 ,  H01L31/03925 ,  H01L31/072 ,  H01L31/073 ,  H01L31/1832 ,  H01L31/1836 ,  Y02E10/543 ,  Y02P70/50

Abstract: A photovoltaic device is presented. The photovoltaic device includes a layer stack; and an absorber layer is disposed on the layer stack. The absorber layer comprises selenium, wherein an atomic concentration of selenium varies across a thickness of the absorber layer. The photovoltaic device is substantially free of a cadmium sulfide layer.

公开(公告)号：US20240021719A1

公开(公告)日：2024-01-18

申请号：US18355299

申请日：2023-07-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chi-Ming CHEN ,  Po-Chun LIU ,  Chung-Yi YU ,  Chia-Shiung TSAI ,  Ru-Liang LEE

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/66462 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/0262 ,  H01L21/02579 ,  H01L21/0254 ,  H01L21/26546

Abstract: A semiconductor device includes a substrate and a seed layer over the substrate. The seed layer includes a first seed sublayer having a first lattice structure, wherein the first seed sublayer includes AlN, and the first seed sublayer is doped with carbon, and a second seed sublayer over the first seed layer, wherein the second seed layer has a second lattice structure different from the first lattice structure, and a thickness of the second seed sublayer ranges from about 50 nanometers (nm) to about 200 nm. The semiconductor device further includes a graded layer over the seed layer. The graded layer includes a first graded sublayer including AlGaN, having a first Al:Ga ratio; and a second graded sublayer over the first graded sublayer, wherein the second graded sublayer includes AlGaN having a second Al:Ga ratio. The semiconductor device further includes a two-dimensional electron gas (2-DEG) over the graded layer.

公开(公告)号：US11859310B2

公开(公告)日：2024-01-02

申请号：US17129737

申请日：2020-12-21

Applicant: AZUR SPACE SOLAR POWER GMBH

Inventor： Clemens Waechter ,  Gregor Keller ,  Daniel Fuhrmann

IPC: C30B29/40 ,  C30B25/14 ,  C30B25/06 ,  C30B25/18 ,  H01L21/02 ,  C30B25/16

CPC classification number: C30B29/40 ,  C30B25/14 ,  C30B25/165 ,  C30B25/18 ,  H01L21/0251 ,  H01L21/0257 ,  H01L21/0262 ,  H01L21/02463 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02576 ,  H01L21/02579

Abstract: A vapor phase epitaxy method of growing a III-V layer with a doping that changes from a first conductivity type to a second conductivity type on a surface of a substrate or a preceding layer in a reaction chamber from the vapor phase from an epitaxial gas flow comprising a carrier gas, at least one first precursor for an element from main group III, and at least one second precursor for an element from main group V, wherein when a first growth height is reached, a first initial doping level of the first conductivity type is set by means of a ratio of a first mass flow of the first precursor to a second mass flow of the second precursor in the epitaxial gas flow, the first initial doping level is then reduced to a second initial doping level of the first or low second conductivity type.

公开(公告)号：US11656231B2

公开(公告)日：2023-05-23

申请号：US15243644

申请日：2016-08-22

Applicant: TECTUS CORPORATION

Inventor： Lianhua Qu ,  Gregory Miller

IPC: G01N33/58 ,  B82Y10/00 ,  H01L21/02 ,  H01L23/29 ,  H01L23/31 ,  B82Y30/00 ,  B82Y40/00 ,  G01N33/533 ,  H01L29/12 ,  H01L29/22 ,  H01L29/221 ,  C09K11/02 ,  C09K11/88 ,  A61K49/00 ,  A61K47/69 ,  H01L29/06 ,  A61K9/51 ,  A61K9/14 ,  H01L33/44 ,  C09K11/56 ,  B82Y5/00 ,  B82Y15/00

CPC classification number: G01N33/588 ,  A61K9/5115 ,  A61K9/5192 ,  A61K47/6923 ,  A61K49/0093 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  C09K11/025 ,  C09K11/565 ,  C09K11/883 ,  G01N33/533 ,  H01L21/0251 ,  H01L21/0256 ,  H01L21/02178 ,  H01L21/02244 ,  H01L21/02557 ,  H01L21/02601 ,  H01L21/02628 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/0665 ,  H01L29/127 ,  H01L29/221 ,  H01L29/2203 ,  A61K9/14 ,  B82Y5/00 ,  B82Y15/00 ,  H01L21/02406 ,  H01L21/02409 ,  H01L21/02521 ,  H01L21/02664 ,  H01L33/44 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10S977/773 ,  Y10S977/774 ,  Y10S977/906 ,  Y10S977/915 ,  Y10S977/927 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Passivated semiconductor nanoparticles and methods for the fabrication and use of passivated semiconductor nanoparticles is provided herein.

公开(公告)号：US20190214468A1

公开(公告)日：2019-07-11

申请号：US16209858

申请日：2018-12-04

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： T. Warren Weeks, JR. ,  Edwin Lanier Piner ,  Thomas Gehrke ,  Kevin J. Linthicum

IPC: H01L29/15 ,  H01L29/205 ,  H01L21/02 ,  H01L33/04 ,  C30B23/02 ,  C30B25/18 ,  C30B29/06 ,  C30B29/68 ,  H01L33/06 ,  H01L29/778 ,  H01L29/78 ,  H01L29/04 ,  H01L29/06 ,  H01L29/201 ,  H01L29/66 ,  H01L33/12 ,  H01L33/00 ,  H01L29/20 ,  H01L29/225 ,  H01L33/32 ,  C30B29/40 ,  C30B25/02

CPC classification number: H01L29/155 ,  C30B23/02 ,  C30B23/025 ,  C30B25/02 ,  C30B25/18 ,  C30B25/183 ,  C30B29/06 ,  C30B29/403 ,  C30B29/406 ,  C30B29/68 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/02598 ,  H01L21/0262 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/225 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/78 ,  H01L33/0066 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/04 ,  H01L33/06 ,  H01L33/12 ,  H01L33/32 ,  Y10T428/24942 ,  Y10T428/26 ,  Y10T428/265

Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

公开(公告)号：US20180247810A1

公开(公告)日：2018-08-30

申请号：US15965065

申请日：2018-04-27

Applicant: NGK INSULATORS, LTD.

Inventor： Mikiya ICHIMURA ,  Sota MAEHARA ,  Yoshitaka KURAOKA

IPC: H01L21/02 ,  C23C16/34 ,  C30B29/40 ,  C30B19/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66

CPC classification number: H01L21/02389 ,  C23C16/303 ,  C23C16/34 ,  C30B19/02 ,  C30B29/406 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/205 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/207 ,  H01L29/401 ,  H01L29/66007 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/812

Abstract: Provided is an epitaxial substrate for semiconductor elements which suppresses an occurrence of current collapse. The epitaxial substrate for the semiconductor elements includes: a semi-insulating free-standing substrate formed of GaN being doped with Zn; a buffer layer being adjacent to the free-standing substrate; a channel layer being adjacent to the buffer layer; and a barrier layer being provided on an opposite side of the buffer layer with the channel layer therebetween, wherein the buffer layer is a diffusion suppressing layer formed of Al-doped GaN and suppresses diffusion of Zn from the free-standing substrate into the channel layer.

公开(公告)号：US09991346B2

公开(公告)日：2018-06-05

申请号：US15501923

申请日：2015-07-22

Applicant: EPIGAN NV

Inventor： Joff Derluyn ,  Stefan Degroote

IPC: H01L29/205 ,  H01L29/66 ,  H01L21/02 ,  H01L29/778 ,  H01L29/20 ,  H01L29/06

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/0688 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: A semiconductor structure includes a buffer layer stack comprising a plurality of III-V material layers, and the buffer layer stack includes at least one layered substructure. Each layered substructure comprises a compressive stress inducing structure between a respective first buffer layer and a respective second buffer layer positioned higher in the buffer layer stack than the respective first buffer layer. A lower surface of the respective second buffer layer has a lower Al content than an upper surface of the respective first buffer layer. An active semiconductor layer of the III-V type is provided on the buffer layer stack. The surface of the respective relaxation layers is sufficiently rough to inhibit the relaxation of the respective second buffer layer, and comprises a Root Mean Square (RMS) roughness larger than 1 nm. A method is provided for producing the semiconductor structure.

公开(公告)号：US09947530B2

公开(公告)日：2018-04-17

申请号：US15399898

申请日：2017-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Jo Tak ,  Sam Mook Kang ,  Mi Hyun Kim ,  Jun Youn Kim ,  Young Soo Park

IPC: H01L21/20 ,  H01L21/205 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L21/0254 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/02513 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/304 ,  H01L21/30604

Abstract: A method of manufacturing a nitride semiconductor substrate includes providing a silicon substrate having a first surface and a second surface opposing each other, growing a nitride template on the first surface of the silicon substrate in a first growth chamber, in which a silicon compound layer is formed on the second surface of the silicon substrate in a growth process of the nitride template, removing the silicon compound layer from the second surface of the silicon substrate, growing a group III nitride single crystal on the nitride template in a second growth chamber, and removing the silicon substrate from the second growth chamber.

公开(公告)号：US09934964B2

公开(公告)日：2018-04-03

申请号：US15095828

申请日：2016-04-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Christopher Leitz ,  Christopher J. Vineis ,  Richard Westhoff ,  Vicky Yang ,  Matthew T. Currie

IPC: H01L21/02 ,  C30B25/02 ,  C30B29/52 ,  H01L21/8238 ,  C30B23/02 ,  C30B23/06 ,  C30B25/18

CPC classification number: H01L21/0251 ,  C30B23/025 ,  C30B23/066 ,  C30B25/02 ,  C30B25/183 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/823807

Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

公开(公告)号：US09818824B2

公开(公告)日：2017-11-14

申请号：US14968049

申请日：2015-12-14

Applicant: Moon Seung Yang ,  Eun Hye Choi ,  Sun Jung Kim ,  Seung Hun Lee ,  Hyun-Jung Lee

Inventor： Moon Seung Yang ,  Eun Hye Choi ,  Sun Jung Kim ,  Seung Hun Lee ,  Hyun-Jung Lee

IPC: H01L29/161 ,  H01L29/10 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02532 ,  H01L29/161 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor substrate and a semiconductor device are provided. The semiconductor substrate includes a base substrate, a first silicon germanium layer on the base substrate and a second silicon germanium layer on the first silicon germanium layer. A germanium fraction of the second silicon germanium layer decreases in the direction away from the base substrate, and a germanium fraction of a lowermost part of the second silicon germanium layer is greater than a germanium fraction of an uppermost part of the first silicon germanium layer.