公开(公告)号：US20170179044A1

公开(公告)日：2017-06-22

申请号：US15008432

申请日：2016-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Tai Hsu ,  Tien-Shang Kuo ,  Yen-Chuan Chen ,  Chih-Hao Cheng

IPC: H01L23/00 ,  H01L23/58 ,  H01L23/544

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L21/784 ,  H01L22/32 ,  H01L23/544 ,  H01L23/585 ,  H01L24/16 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L2223/5446 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05096 ,  H01L2224/05567 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/82047 ,  H01L2224/821 ,  H01L2224/92124 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/82

Abstract: An integrated circuit includes a scribe line, a bonding pad structure and an extension pad structure. The scribe line is disposed on a substrate, and the bonding pad structure and the extension pad structure are both disposed in a dielectric layer on the substrate. The bonding pad structure includes first vias disposed on first metal layers in the dielectric layer. The extension pad structure includes second metal layers and a number of the second metal layer is less than that of the first metal layers. Also, the bonding pad structure has a first region and a second region, and second vias is disposed on the second metal layers in the first region and no vias is disposed on the second metal layers in the second region.

公开(公告)号：US09941220B2

公开(公告)日：2018-04-10

申请号：US15008432

申请日：2016-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Tai Hsu ,  Tien-Shang Kuo ,  Yen-Chuan Chen ,  Chih-Hao Cheng

IPC: H01L23/00 ,  H01L23/544 ,  H01L23/58 ,  H01L21/784 ,  H01L21/66

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L21/784 ,  H01L22/32 ,  H01L23/544 ,  H01L23/585 ,  H01L24/16 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L2223/5446 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05096 ,  H01L2224/05567 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/82047 ,  H01L2224/821 ,  H01L2224/92124 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/82

Abstract: An integrated circuit includes a scribe line, a bonding pad structure and an extension pad structure. The scribe line is disposed on a substrate, and the bonding pad structure and the extension pad structure are both disposed in a dielectric layer on the substrate. The bonding pad structure includes first vias disposed on first metal layers in the dielectric layer. The extension pad structure includes second metal layers and a number of the second metal layer is less than that of the first metal layers. Also, the bonding pad structure has a first region and a second region, and second vias is disposed on the second metal layers in the first region and no vias is disposed on the second metal layers in the second region.