公开(公告)号：US10727234B2

公开(公告)日：2020-07-28

申请号：US15361479

申请日：2016-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen ,  Xing Hua Zhang ,  Shan Liu ,  Runshun Wang ,  Chien-Fu Chen ,  Wei-Jen Wang ,  Chen-Hsien Hsu

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L27/02 ,  H01L21/8238

Abstract: The present invention provides a layout of a semiconductor transistor device including a first and a second active area, a first and a second gate, and a metal line. The first active and the second active area are extended along a first direction. The first gate and the second gate are extended along a second direction and crossed the first active area, to define two transistors. The two transistors are electrically connected with each other through a conductive layer. The metal line is disposed on the conductive layer and is electrically connected the two transistors respectively.

公开(公告)号：US20180151571A1

公开(公告)日：2018-05-31

申请号：US15361479

申请日：2016-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Ding-Lung Chen ,  Xing Hua Zhang ,  Shan Liu ,  RUNSHUN WANG ,  Chien-Fu Chen ,  Wei-Jen Wang ,  Chen-Hsien Hsu

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/06

Abstract: The present invention provides a layout of a semiconductor transistor device including a first and a second active area, a first and a second gate, and a metal line. The first active and the second active area are extended along a first direction. The first gate and the second gate are extended along a second direction and crossed the first active area, to define two transistors. The two transistors are electrically connected with each other through a conductive layer. The metal line is disposed on the conductive layer and is electrically connected the two transistors respectively.