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公开(公告)号:US20140035111A1
公开(公告)日:2014-02-06
申请号:US14062914
申请日:2013-10-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Meng-Ping Chuang , Yu-Tse Kuo , Chia-Chun Sun , Yun-San Huang
IPC: H01L29/06
CPC classification number: H01L29/0692 , H01L27/0207 , H01L27/1104 , H01L29/0684
Abstract: A layout configuration for a memory cell array includes at least a comb-like doped region having a first conductivity type and a fishbone-shaped doped region having a second conductivity type. The second conductivity type and the first conductivity type are complementary. Furthermore, the comb-like doped region and the fishbone-shaped doped region are interdigitated.
Abstract translation: 存储单元阵列的布局配置至少包括具有第一导电类型的梳状掺杂区域和具有第二导电类型的鱼骨形掺杂区域。 第二导电类型和第一导电类型是互补的。 此外,梳状掺杂区域和鱼骨形掺杂区域是交错的。
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公开(公告)号:US09166003B2
公开(公告)日:2015-10-20
申请号:US14062914
申请日:2013-10-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Meng-Ping Chuang , Yu-Tse Kuo , Chia-Chun Sun , Yun-San Huang
CPC classification number: H01L29/0692 , H01L27/0207 , H01L27/1104 , H01L29/0684
Abstract: A layout configuration for a memory cell array includes at least a comb-like doped region having a first conductivity type and a fishbone-shaped doped region having a second conductivity type. The second conductivity type and the first conductivity type are complementary. Furthermore, the comb-like doped region and the fishbone-shaped doped region are interdigitated.
Abstract translation: 存储单元阵列的布局配置至少包括具有第一导电类型的梳状掺杂区域和具有第二导电类型的鱼骨形掺杂区域。 第二导电类型和第一导电类型是互补的。 此外,梳状掺杂区域和鱼骨形掺杂区域是交错的。
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