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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US10090308B1

    公开(公告)日：2018-10-02

    申请号：US15498464

    申请日：2017-04-26

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Chien-Hung Chen ,  Meng-Ping Chuang ,  Hsueh-Hao Shih

    IPC分类号： H01L27/11 ,  H01L27/02 ,  H01L27/092 ,  H01L23/528 ,  G11C11/417

    摘要： A semiconductor memory device having a memory cell including a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type well region disposed between the first P-Type well region and the second P-type well region. The semiconductor memory element defines a plurality of first regions, a plurality of second regions, a plurality of third regions, and a plurality of fourth regions, and each first region includes the memory cell. Each second region, each third region and each fourth region include a voltage contact to provide a voltage to the first P-type well region, the second P-type well region, and the N-type well region. The first region to the fourth region do not overlap with each other.

    Layout of semiconductor memory device
    2.
    发明授权
    Layout of semiconductor memory device 有权

    公开(公告)号：US11915755B2

    公开(公告)日：2024-02-27

    申请号：US17580591

    申请日：2022-01-20

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Chun-Yen Tseng ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Hsien Huang ,  Hsin-Chih Yu ,  Meng-Ping Chuang ,  Li-Ping Huang ,  Yu-Fang Chen

    IPC分类号： G11C15/04

    CPC分类号： G11C15/04

    摘要： A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US10134449B2

    公开(公告)日：2018-11-20

    申请号：US15589985

    申请日：2017-05-08

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Chien-Hung Chen ,  Meng-Ping Chuang ,  Tong-Yu Chen ,  Yu-Tse Kuo

    IPC分类号： G11C5/02 ,  G11C11/412 ,  H01L27/11

    摘要： A semiconductor memory device including a memory cell having a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type well region disposed between the first P-Type well region and the second P-type well region. The semiconductor memory element defines a plurality of first regions and a plurality of second regions, each of the first regions and each of the second regions including one of the memory cells, each of the second regions further includes at least two first voltage providing contacts, and at least one second voltage providing contact, wherein the first voltage providing contacts and the second voltage providing contact are not located within each first region.

    SEMICONDUCTOR MEMORY DEVICE
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20180286474A1

    公开(公告)日：2018-10-04

    申请号：US15589985

    申请日：2017-05-08

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Chien-Hung Chen ,  Meng-Ping Chuang ,  Tong-Yu Chen ,  Yu-Tse Kuo

    IPC分类号： G11C11/406 ,  G11C11/407

    CPC分类号： G11C5/025 ,  G11C11/412 ,  H01L27/11 ,  H01L27/1104

    摘要： A semiconductor memory device including a memory cell having a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type well region disposed between the first P-Type well region and the second P-type well region. The semiconductor memory element defines a plurality of first regions and a plurality of second regions, each of the first regions and each of the second regions including one of the memory cells, each of the second regions further includes at least two first voltage providing contacts, and at least one second voltage providing contact, wherein the first voltage providing contacts and the second voltage providing contact are not located within each first region.

    Layout configuration for memory cell array
    5.
    发明授权
    Layout configuration for memory cell array 有权
    存储单元阵列的布局配置

    公开(公告)号：US09166003B2

    公开(公告)日：2015-10-20

    申请号：US14062914

    申请日：2013-10-25

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Meng-Ping Chuang ,  Yu-Tse Kuo ,  Chia-Chun Sun ,  Yun-San Huang

    IPC分类号： H01L29/06 ,  H01L27/02 ,  H01L27/11

    CPC分类号： H01L29/0692 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/0684

    摘要： A layout configuration for a memory cell array includes at least a comb-like doped region having a first conductivity type and a fishbone-shaped doped region having a second conductivity type. The second conductivity type and the first conductivity type are complementary. Furthermore, the comb-like doped region and the fishbone-shaped doped region are interdigitated.

    摘要翻译： 存储单元阵列的布局配置至少包括具有第一导电类型的梳状掺杂区域和具有第二导电类型的鱼骨形掺杂区域。 第二导电类型和第一导电类型是互补的。 此外，梳状掺杂区域和鱼骨形掺杂区域是交错的。

    LAYOUT OF SEMICONDUCTOR MEMORY DEVICE
    6.
    发明公开
    LAYOUT OF SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230197153A1

    公开(公告)日：2023-06-22

    申请号：US17580591

    申请日：2022-01-20

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Chun-Yen Tseng ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Hsien Huang ,  Hsin-Chih Yu ,  Meng-Ping Chuang ,  Li-Ping Huang ,  Yu-Fang Chen

    IPC分类号： G11C15/04

    CPC分类号： G11C15/04

    摘要： A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

    STATIC RANDOM ACCESS MEMORY STRUCTURE
    9.
    发明申请
    STATIC RANDOM ACCESS MEMORY STRUCTURE 审中-公开

    公开(公告)号：US20190096892A1

    公开(公告)日：2019-03-28

    申请号：US16162340

    申请日：2018-10-16

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Shu-Ru Wang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chien-Hung Chen ,  Chun-Hsien Huang ,  Li-Ping Huang ,  Chun-Yen Tseng ,  Meng-Ping Chuang

    IPC分类号： H01L27/11 ,  G11C11/412 ,  G11C7/18 ,  G11C8/14 ,  G11C5/06

    摘要： A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise a first fin structure, the PG2A and the PG2B comprise a second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2, the first local interconnection layer and the second local interconnection layer are monolithically formed structures respectively.