公开(公告)号：US20210273356A1

公开(公告)日：2021-09-02

申请号：US17322906

申请日：2021-05-18

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang TSENG ,  Pei-Wei WANG ,  Ching-Ho HSIEH ,  Shao-Chien LEE ,  Kuo-Wei LI

IPC: H01R12/62 ,  H05K1/02 ,  H05K1/14 ,  H05K1/11 ,  H05K1/03 ,  H05K3/00 ,  H05K3/40 ,  H05K3/46

Abstract: A circuit board structure has a first flexible circuit board, a second flexible circuit board, and a rigid board structure. The first flexible circuit board has a first dielectric layer and a first conductive circuit. The second flexible circuit board has a second dielectric layer and a second conductive circuit. The rigid board structure connects the first flexible circuit board and the second flexible circuit board. The rigid board structure has a third dielectric layer and a third conductive circuit. A dielectric loss value of the third dielectric layer is less than that of each of the first dielectric layer and the second dielectric layer. The third conductive circuit is electrically connected to the first and second conductive circuits.

公开(公告)号：US20220071010A1

公开(公告)日：2022-03-03

申请号：US17448893

申请日：2021-09-26

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang TSENG ,  Cheng-Ta KO ,  Pu-Ju LIN ,  Chi-Hai KUO ,  Shao-Chien LEE ,  Ming-Ru CHEN ,  Cheng-Chung LO

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/00

Abstract: A circuit board structure includes a first sub-circuit board, a second sub-circuit board, and a third sub-circuit board. The first sub-circuit board has an upper surface and a lower surface opposite to each other, and includes at least one first conductive through hole. The second sub-circuit board is disposed on the upper surface of the first sub-circuit board and includes at least one second conductive through hole. The third sub-circuit board is disposed on the lower surface of the first sub-circuit board and includes at least one third conductive through hole. At least two of the first conductive through hole, the second conductive through hole, and the third conductive through hole are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first, second and third sub-circuit boards are electrically connected to one another.

公开(公告)号：US20240306298A1

公开(公告)日：2024-09-12

申请号：US18668275

申请日：2024-05-20

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang TSENG ,  Cheng-Ta KO ,  Pu-Ju LIN ,  Chi-Hai KUO ,  Shao-Chien LEE ,  Ming-Ru CHEN ,  Cheng-Chung LO

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/00

CPC classification number: H05K1/115 ,  H05K1/0306 ,  H05K3/0067 ,  H05K3/0094

Abstract: A manufacturing method of a circuit board structure includes the following steps. A first sub-circuit board having an upper surface and a lower surface opposite to each other and including at least one conductive through hole is provided. A second sub-circuit board including at least one conductive through hole is provided on the upper surface of the first sub-circuit board. A third sub-circuit board including at least one conductive through hole is provided on the lower surface of the first sub-circuit board. The first sub-circuit board, the second sub-circuit board, and the third sub-circuit board are laminated so that at least two of their conductive through holes are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first sub-circuit board, the second sub-circuit board, and the third sub-circuit board are electrically connected to one another.

公开(公告)号：US20240023251A1

公开(公告)日：2024-01-18

申请号：US17899467

申请日：2022-08-30

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Shao-Chien LEE ,  Ching-Sheng CHEN ,  Heng-Ming NIEN ,  Pei-Wei WANG

IPC: H05K3/46 ,  H05K3/40 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K3/4679 ,  H05K3/4046 ,  H05K1/0298 ,  H05K1/116 ,  H05K2203/016 ,  H05K2203/1131

Abstract: A manufacturing method for circuit board structure includes steps of providing a carrier, forming a first build-up layer including a plurality of first circuits, forming a second build-up layer including a plurality of second circuits on a side of the first build-up layer located away from the carrier, attaching a side of the second build-up layer located away from the first build-up layer to a core layer, and removing the carrier from the first build-up layer, where the first circuits are finer than the second circuits.