公开(公告)号：US20240145412A1

公开(公告)日：2024-05-02

申请号：US17994382

申请日：2022-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Che Huang ,  Chao-Ting Chen ,  Jui-Fa Lu ,  Chi-Heng Lin

IPC: H01L23/60 ,  H01L23/522

CPC classification number: H01L23/60 ,  H01L23/5221 ,  H01L23/5226

Abstract: A semiconductor device includes a logic circuit region having at least one core device and at least one input/output (I/O) device. The at least one core device has a first accumulative antenna ratio, and the at least one I/O device has a second accumulative antenna ratio. The first accumulative antenna ratio is greater than the second accumulative antenna ratio.

公开(公告)号：US20230050928A1

公开(公告)日：2023-02-16

申请号：US17472577

申请日：2021-09-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Che Huang ,  Ching-Chih Chang ,  Yuan-Fu Ko ,  Chih-Sheng Chang

IPC: H01L23/528 ,  H01L23/522

Abstract: A semiconductor device includes a first metal interconnection disposed on a substrate, a second metal interconnection disposed on the first metal interconnection, a first contact via disposed between the first metal interconnection and the second metal interconnection, a first serpent metal line connecting to a first end of the first metal interconnection, and a second serpent metal line connecting to a second end of the first metal interconnection. Preferably, the first serpent metal line, the second serpent metal line, and the first metal interconnection are on a same level.

公开(公告)号：US10978391B2

公开(公告)日：2021-04-13

申请号：US15730744

申请日：2017-10-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Yi Weng ,  Shih-Che Huang ,  Ching-Li Yang ,  Chih-Sheng Chang

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L23/498

Abstract: A connection structure of a semiconductor device is provided in the present invention. The connection structure includes an interlayer dielectric, a top metal structure, and a passivation layer. The interlayer dielectric is disposed on a substrate. The top metal structure is disposed on the interlayer dielectric. The top metal structure includes a bottom portion and a top portion disposed on the bottom portion. The bottom portion includes a first sidewall, and the top portion includes a second sidewall. A slope of the first sidewall is larger than a slope of the second sidewall. The passivation layer is conformally disposed on the second sidewall, the first sidewall, and a top surface of the interlayer dielectric.

公开(公告)号：US20200066657A1

公开(公告)日：2020-02-27

申请号：US16135997

申请日：2018-09-19

Applicant: United Microelectronics Corp.

Inventor： Shih-Che Huang ,  Shih-Hsien Chen ,  Ching-Li Yang ,  Chih-Sheng Chang

IPC: H01L23/58 ,  H01L23/10 ,  H01L23/00 ,  H01L21/48 ,  H01L23/522

Abstract: A die seal ring and a manufacturing method thereof are provided. The die seal ring includes a substrate, a dielectric layer, and conductive layers. The dielectric layer is disposed on the substrate. The conductive layers are stacked on the substrate and located in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is disposed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is disposed between a sidewall of the second conductive portion and the dielectric layer. The die seal ring and the manufacturing method thereof can effectively prevent cracks generated during the die sawing process from damaging the circuit structure.

公开(公告)号：US11916018B2

公开(公告)日：2024-02-27

申请号：US17191730

申请日：2021-03-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Yi Weng ,  Shih-Che Huang ,  Ching-Li Yang ,  Chih-Sheng Chang

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L23/49838 ,  H01L23/5228 ,  H01L23/53214 ,  H01L23/5222 ,  H01L23/5329

Abstract: A connection structure of a semiconductor device is provided in the present invention. The connection structure includes an interlayer dielectric, a top metal structure, and a passivation layer. The interlayer dielectric is disposed on a substrate. The top metal structure is disposed on the interlayer dielectric. The top metal structure includes a bottom portion and a top portion disposed on the bottom portion. The bottom portion includes a first sidewall, and the top portion includes a second sidewall. A slope of the first sidewall is larger than a slope of the second sidewall. The passivation layer is conformally disposed on the second sidewall, the first sidewall, and a top surface of the interlayer dielectric.

公开(公告)号：US11664333B2

公开(公告)日：2023-05-30

申请号：US17103584

申请日：2020-11-24

Applicant: United Microelectronics Corp.

Inventor： Shih-Che Huang ,  Shih-Hsien Chen ,  Ching-Li Yang ,  Chih-Sheng Chang

IPC: H01L21/48 ,  H01L21/768 ,  H01L23/58 ,  H01L23/10 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L23/585 ,  H01L21/4846 ,  H01L21/7682 ,  H01L23/10 ,  H01L23/522 ,  H01L23/562 ,  H01L21/76807

Abstract: A method of manufacturing a die seal ring including the following steps is provided. A dielectric layer is formed on a substrate. Conductive layers stacked on the substrate are formed in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is formed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is formed between a sidewall of the second conductive portion and the dielectric layer.

公开(公告)号：US20210193575A1

公开(公告)日：2021-06-24

申请号：US17191730

申请日：2021-03-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Yi Weng ,  Shih-Che Huang ,  Ching-Li Yang ,  Chih-Sheng Chang

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/498 ,  H01L23/522

Abstract: A connection structure of a semiconductor device is provided in the present invention. The connection structure includes an interlayer dielectric, a top metal structure, and a passivation layer. The interlayer dielectric is disposed on a substrate. The top metal structure is disposed on the interlayer dielectric. The top metal structure includes a bottom portion and a top portion disposed on the bottom portion. The bottom portion includes a first sidewall, and the top portion includes a second sidewall. A slope of the first sidewall is larger than a slope of the second sidewall. The passivation layer is conformally disposed on the second sidewall, the first sidewall, and a top surface of the interlayer dielectric.

公开(公告)号：US10892235B2

公开(公告)日：2021-01-12

申请号：US16135997

申请日：2018-09-19

Applicant: United Microelectronics Corp.

Inventor： Shih-Che Huang ,  Shih-Hsien Chen ,  Ching-Li Yang ,  Chih-Sheng Chang

IPC: H01L21/764 ,  H01L21/768 ,  H01L23/58 ,  H01L23/10 ,  H01L23/522 ,  H01L21/48 ,  H01L23/00

Abstract: A die seal ring and a manufacturing method thereof are provided. The die seal ring includes a substrate, a dielectric layer, and conductive layers. The dielectric layer is disposed on the substrate. The conductive layers are stacked on the substrate and located in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is disposed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is disposed between a sidewall of the second conductive portion and the dielectric layer. The die seal ring and the manufacturing method thereof can effectively prevent cracks generated during the die sawing process from damaging the circuit structure.

公开(公告)号：US20210082839A1

公开(公告)日：2021-03-18

申请号：US17103584

申请日：2020-11-24

Applicant: United Microelectronics Corp.

Inventor： Shih-Che Huang ,  Shih-Hsien Chen ,  Ching-Li Yang ,  Chih-Sheng Chang

IPC: H01L23/58 ,  H01L23/10 ,  H01L23/522 ,  H01L21/48 ,  H01L23/00 ,  H01L21/768

Abstract: A method of manufacturing a die seal ring including the following steps is provided. A dielectric layer is formed on a substrate. Conductive layers stacked on the substrate are formed in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is formed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is formed between a sidewall of the second conductive portion and the dielectric layer.

公开(公告)号：US20190081000A1

公开(公告)日：2019-03-14

申请号：US15730744

申请日：2017-10-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Yi Weng ,  Shih-Che Huang ,  Ching-Li Yang ,  Chih-Sheng Chang

IPC: H01L23/532 ,  H01L23/522

Abstract: A connection structure of a semiconductor device is provided in the present invention. The connection structure includes an interlayer dielectric, a top metal structure, and a passivation layer. The interlayer dielectric is disposed on a substrate. The top metal structure is disposed on the interlayer dielectric. The top metal structure includes a bottom portion and a top portion disposed on the bottom portion. The bottom portion includes a first sidewall, and the top portion includes a second sidewall. A slope of the first sidewall is larger than a slope of the second sidewall. The passivation layer is conformally disposed on the second sidewall, the first sidewall, and a top surface of the interlayer dielectric.