公开(公告)号：US11545484B2

公开(公告)日：2023-01-03

申请号：US17150960

申请日：2021-01-15

Applicant: United Microelectronics Corp.

Inventor： Jui-Fa Lu ,  Chien-Nan Lin ,  Ching-Hua Yeh

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/49 ,  H01L23/528 ,  H01L29/66 ,  H01L23/532 ,  H01L49/02 ,  H01L23/522 ,  G06F30/39 ,  G06F30/392 ,  G06F119/18

Abstract: A design method of a dummy pattern layout including the following steps is provided. An integrated circuit layout design including resistor elements is obtained via a computer. The locations of dummy conductive structures are configured, wherein the dummy conductive structures are aligned with the resistor elements. The locations of dummy support patterns are configured, wherein each of the dummy support patterns is configured between two adjacent dummy conductive structures, and each of the dummy conductive structures is equidistant from the dummy support patterns on both sides.

公开(公告)号：US20160133559A1

公开(公告)日：2016-05-12

申请号：US14537913

申请日：2014-11-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jui-Fa Lu ,  Chin-Chun Huang ,  Chun-Nien Chen

IPC: H01L23/528 ,  H01L29/423 ,  H01L21/768 ,  H01L21/22 ,  H01L49/02 ,  H01L27/06

CPC classification number: H01L29/42372 ,  H01L21/22 ,  H01L23/522 ,  H01L27/0617 ,  H01L27/0629 ,  H01L28/10 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a substrate comprising a plurality of layers formed thereon, at least a first device formed in one of the layers formed thereon, a drawn region enclosing the first device, and a plurality of dummy structures in another layer. The dummy structures are formed in a first region correspondingly outside of the drawing region and in a second region correspondingly inside of the drawing region.

Abstract translation: 一种半导体结构，包括：在其上形成有多个层的至少第一器件，形成在其中的一个层中的第一器件，包围第一器件的引出区域，以及另一层中的多个虚设结构。 虚拟结构形成在对应于绘制区域外部的第一区域和对应于绘图区域内的第二区域中。

公开(公告)号：US20240145412A1

公开(公告)日：2024-05-02

申请号：US17994382

申请日：2022-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Che Huang ,  Chao-Ting Chen ,  Jui-Fa Lu ,  Chi-Heng Lin

IPC: H01L23/60 ,  H01L23/522

CPC classification number: H01L23/60 ,  H01L23/5221 ,  H01L23/5226

Abstract: A semiconductor device includes a logic circuit region having at least one core device and at least one input/output (I/O) device. The at least one core device has a first accumulative antenna ratio, and the at least one I/O device has a second accumulative antenna ratio. The first accumulative antenna ratio is greater than the second accumulative antenna ratio.

公开(公告)号：US20210134790A1

公开(公告)日：2021-05-06

申请号：US17150960

申请日：2021-01-15

Applicant: United Microelectronics Corp.

Inventor： Jui-Fa Lu ,  Chien-Nan Lin ,  Ching-Hua Yeh

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/49 ,  H01L23/528 ,  H01L29/66 ,  H01L23/532 ,  H01L49/02 ,  H01L23/522 ,  G06F30/39 ,  G06F30/392

Abstract: A design method of a dummy pattern layout including the following steps is provided. An integrated circuit layout design including resistor elements is obtained via a computer. The locations of dummy conductive structures are configured, wherein the dummy conductive structures are aligned with the resistor elements. The locations of dummy support patterns are configured, wherein each of the dummy support patterns is configured between two adjacent dummy conductive structures, and each of the dummy conductive structures is equidistant from the dummy support patterns on both sides.

公开(公告)号：US10964689B2

公开(公告)日：2021-03-30

申请号：US15705026

申请日：2017-09-14

Applicant: United Microelectronics Corp.

Inventor： Jui-Fa Lu ,  Chien-Nan Lin ,  Ching-Hua Yeh

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/49 ,  H01L23/528 ,  H01L29/66 ,  H01L23/532 ,  H01L49/02 ,  H01L23/522 ,  G06F30/39 ,  G06F30/392 ,  G06F119/18

Abstract: A semiconductor structure including a substrate, dummy conductive structures, and resistor elements is provided. The substrate includes a resistor region and has isolation structures and dummy support patterns located in the resistor region. Each of the isolation structures is located between two adjacent dummy support patterns. Each of the dummy conductive structures is disposed on each of the isolation structures and equidistant from the dummy support patterns on both sides. The resistor elements are disposed above the dummy conductive structures and aligned with the dummy conductive structures.

公开(公告)号：US20190057962A1

公开(公告)日：2019-02-21

申请号：US15705026

申请日：2017-09-14

Applicant: United Microelectronics Corp.

Inventor： Jui-Fa Lu ,  Chien-Nan Lin ,  Ching-Hua Yeh

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/49 ,  H01L23/532 ,  H01L23/528 ,  H01L29/66 ,  G06F17/50

Abstract: A semiconductor structure including a substrate, dummy conductive structures, and resistor elements is provided. The substrate includes a resistor region and has isolation structures and dummy support patterns located in the resistor region. Each of the isolation structures is located between two adjacent dummy support patterns. Each of the dummy conductive structures is disposed on each of the isolation structures and equidistant from the dummy support patterns on both sides. The resistor elements are disposed above the dummy conductive structures and aligned with the dummy conductive structures.