公开(公告)号：US20150008529A1

公开(公告)日：2015-01-08

申请号：US13937142

申请日：2013-07-08

Applicant: United Microelectronics Corp.

Inventor： Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L27/06

CPC classification number: H01L27/0277

Abstract: Provided is an electrostatic discharge (ESD) protection structure including a substrate, a pick-up region, a first MOS device, a second MOS device, a first doped region and a second doped region. The pick-up region is located in the substrate. The first MOS device has a first drain region of a first conductivity type located in the substrate. The second MOS device has a second drain region of the first conductivity type located in the substrate. The first drain region is closer to the pick up region than the second drain region is. The first doped region of a second conductivity type is located under the first doped region. The second doped region of the second conductivity type is located under the second doped region. The area and/or doping concentration of the first doped region is greater than that of the second doped region.

Abstract translation: 提供一种包括基板，拾取区域，第一MOS器件，第二MOS器件，第一掺杂区域和第二掺杂区域的静电放电（ESD）保护结构。 拾取区域位于基板中。 第一MOS器件具有位于衬底中的第一导电类型的第一漏极区域。 第二MOS器件具有位于衬底中的第一导电类型的第二漏极区域。 第一漏极区域比第二漏极区域更靠近拾取区域。 第二导电类型的第一掺杂区位于第一掺杂区的下方。 第二导电类型的第二掺杂区位于第二掺杂区的下方。 第一掺杂区域的面积和/或掺杂浓度大于第二掺杂区域的面积和/或掺杂浓度。

公开(公告)号：US20150137255A1

公开(公告)日：2015-05-21

申请号：US14082529

申请日：2013-11-18

Applicant: United Microelectronics Corp.

Inventor： Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L27/0277 ,  H01L27/088

Abstract: A semiconductor device is described, including a substrate including a first area and a second area, a first MOS element of a first conductivity type in the first area, and a second MOS element of the first conductivity type in the second area. The first area is closer to a pick-up region of the substrate than the second area. The substrate has a second conductivity type. The bottom depth of a first electrical conduction path in the substrate in the first area is smaller than that of a second electrical conduction path in the substrate in the second area.

Abstract translation: 描述了一种半导体器件，包括包括第一区域和第二区域的衬底，第一区域中的第一导电类型的第一MOS元件和第二区域中的第一导电类型的第二MOS元件。 第一区域比第二区域更靠近基板的拾取区域。 衬底具有第二导电类型。 第一区域中的衬底中的第一导电通路的底部深度小于第二区域中的衬底中的第二导电通路的深度。

公开(公告)号：US09449960B2

公开(公告)日：2016-09-20

申请号：US13937142

申请日：2013-07-08

Applicant: United Microelectronics Corp.

Inventor： Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang

IPC: H01L21/70 ,  H01L27/02

CPC classification number: H01L27/0277

Abstract: Provided is an electrostatic discharge (ESD) protection structure including a substrate, a pick-up region, a first MOS device, a second MOS device, a first doped region and a second doped region. The pick-up region is located in the substrate. The first MOS device has a first drain region of a first conductivity type located in the substrate. The second MOS device has a second drain region of the first conductivity type located in the substrate. The first drain region is closer to the pick up region than the second drain region is. The first doped region of a second conductivity type is located under the first doped region. The second doped region of the second conductivity type is located under the second doped region. The area and/or doping concentration of the first doped region is greater than that of the second doped region.

Abstract translation: 提供一种包括基板，拾取区域，第一MOS器件，第二MOS器件，第一掺杂区域和第二掺杂区域的静电放电（ESD）保护结构。 拾取区域位于基板中。 第一MOS器件具有位于衬底中的第一导电类型的第一漏极区域。 第二MOS器件具有位于衬底中的第一导电类型的第二漏极区域。 第一漏极区域比第二漏极区域更靠近拾取区域。 第二导电类型的第一掺杂区位于第一掺杂区的下方。 第二导电类型的第二掺杂区位于第二掺杂区的下方。 第一掺杂区域的面积和/或掺杂浓度大于第二掺杂区域的面积和/或掺杂浓度。

公开(公告)号：US09564436B2

公开(公告)日：2017-02-07

申请号：US14082529

申请日：2013-11-18

Applicant: United Microelectronics Corp.

Inventor： Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H02H9/04 ,  H01L27/092 ,  H01L27/02 ,  H01L27/088

CPC classification number: H01L27/092 ,  H01L27/0277 ,  H01L27/088

Abstract: A semiconductor device is described, including a substrate including a first area and a second area, a first MOS element of a first conductivity type in the first area, and a second MOS element of the first conductivity type in the second area. The first area is closer to a pick-up region of the substrate than the second area. The substrate has a second conductivity type. The bottom depth of a first electrical conduction path in the substrate in the first area is smaller than that of a second electrical conduction path in the substrate in the second area.

Abstract translation: 描述了一种半导体器件，包括包括第一区域和第二区域的衬底，第一区域中的第一导电类型的第一MOS元件和第二区域中的第一导电类型的第二MOS元件。 第一区域比第二区域更靠近基板的拾取区域。 衬底具有第二导电类型。 第一区域中的衬底中的第一导电通路的底部深度小于第二区域中的衬底中的第二导电通路的深度。

公开(公告)号：US08981488B1

公开(公告)日：2015-03-17

申请号：US14072976

申请日：2013-11-06

Applicant: United Microelectronics Corp.

Inventor： Yung-Ju Wen ,  Tien-Hao Tang ,  Chang-Tzu Wang

IPC: H01L21/70 ,  H01L27/092

CPC classification number: H01L27/088 ,  H01L21/823481 ,  H01L21/823493

Abstract: A semiconductor structure and an integrated circuit are provided. The semiconductor structure includes a first field-effect transistor (FET), a second FET, an isolation structure, and a body electrode. The first FET includes a first active body having a first type conductivity. The second FET includes a second active body having the first type conductivity. The first active body and the second active body are isolated from each other by the isolation structure. The body electrode has the first type conductivity and formed in the second active body.

Abstract translation: 提供半导体结构和集成电路。 半导体结构包括第一场效应晶体管（FET），第二FET，隔离结构和体电极。 第一FET包括具有第一类型导电性的第一有源体。 第二FET包括具有第一类型导电性的第二有源体。 第一活性体和第二活性体通过隔离结构彼此隔离。 主体电极具有第一类型的导电性并且形成在第二主动体中。