公开(公告)号：US11189611B2

公开(公告)日：2021-11-30

申请号：US16844986

申请日：2020-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Jui Chen ,  Po-Ya Lai

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/10

Abstract: An ESD protection semiconductor device includes a substrate. A gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins having a first conductivity type are disposed in the substrate respectively at two sides of the gate set. A first doped fin is disposed in the substrate and positioned in between the source fins and spaced apart from the source fins. The first doped fin comprises a second conductivity type that is complementary to the first conductivity type. A second doped fin is formed in one of the drain fins and isolated from the one of the drain fins by an isolation structure. The second doped fin is electrically connected to the first doped fin.

公开(公告)号：US10978442B2

公开(公告)日：2021-04-13

申请号：US16446599

申请日：2019-06-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ying-Wei Tseng ,  Chun Chiang ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02

Abstract: An electrostatic discharge (ESD) protection device and a method thereof are presented. A well is disposed in a substrate. A gate is disposed on the well. A source region and a drain region are located in the well and at two opposite sides of the gate respectively. A first doped region is located in the drain region, wherein the first doped region is electrically connected to the drain region. A second doped region is located in the source region, wherein the second doped region is electrically connected to the source region. A third doped region is located in the well and at a side of the drain region opposite to the gate. A fourth doped region is located in the well and at a side of the source region opposite to the gate, wherein the fourth doped region is electrically connected to the third doped region.

公开(公告)号：US20180158902A1

公开(公告)日：2018-06-07

申请号：US15402204

申请日：2017-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hou-Jen Chiu ,  Ya-Ting Lin ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0638 ,  H01L29/0653 ,  H01L29/7851

Abstract: A semiconductor device comprises a fin shaped structure, a shallow trench isolation, a diffusion break structure and a gate electrode. The fin shaped structure is disposed on a substrate. The shallow trench isolation is disposed in the substrate and surrounds the fin shaped structure. The diffusion break structure is disposed in the fin shaped structure, and the gate electrode is disposed across the fin shaped structure.

公开(公告)号：US09972615B1

公开(公告)日：2018-05-15

申请号：US15351413

申请日：2016-11-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhih-Ming Wang ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L27/0266 ,  H01L27/0262 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/7835

Abstract: A semiconductor device for ESD protection, includes a drain region, a first doped region, a second doped region and a source region. The drain region is disposed in a substrate at a first side of a gate and the drain region has a first conductivity type. The first doped region is disposed in a second doped well at a second side of the gate and has a second conductivity type. The source region is also disposed in the second doped well and has the first conductive type, and the source region surrounds the first doped region from a topview. The second doped region is disposed in the second doped well and has the second conductive type, and the second doped region is disposed between the gate and the source region, wherein a plurality of contacts is electrically connected to the second doped region.

公开(公告)号：US20170323880A1

公开(公告)日：2017-11-09

申请号：US15188962

申请日：2016-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Yu Tai ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/06

CPC classification number: H01L27/0277 ,  H01L29/0623 ,  H01L29/0653

Abstract: A semiconductor device for electrostatic discharge (ESD) protection includes a doped well, a drain region, a source region, a first doped region and a guard ring. The doped well is disposed in a substrate and has a first conductive type. The drain region is disposed in the doped well and has a second conductive type. The source region is disposed in the doped well and has the second conductive type, wherein the source region is separated from the drain region. The doped region is disposed in the doped well between the drain region and the source region, wherein the doped region has the first conductive type and is in contact with the doped well and the source region. The guard ring is disposed in the doped well and has the first conductive type.

公开(公告)号：US09653450B2

公开(公告)日：2017-05-16

申请号：US14938850

申请日：2015-11-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Jui Chen ,  Po-Ya Lai

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0255 ,  H01L27/0207 ,  H01L27/027 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/7819 ,  H01L29/7831 ,  H01L29/7835 ,  H01L29/785 ,  H01L29/7851

Abstract: An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, and at least a first doped region formed in the drain region. The source region and the drain region include a first conductivity type, and the first doped region includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. The first doped region is electrically connected to a ground potential.

公开(公告)号：US09607980B1

公开(公告)日：2017-03-28

申请号：US15011681

申请日：2016-02-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhih-Ming Wang ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L29/66 ,  H01L27/02 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L27/0266 ,  H01L29/0623 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7826

Abstract: The present invention provides a high voltage transistor including a substrate, a first base region having a first conductivity type, and a first doped region, a second doped region, a second base region and a third doped region having a second conductivity type complementary to the first conductivity type. The first base region, the second doped region, the second base region and the third doped region are disposed in the substrate, and the first doped region is disposed in the substrate. The third doped region, the second base region and the second doped region are stacked sequentially, and the doping concentrations of the third doped region, the second base region and the second doped region gradually increase.

公开(公告)号：US20160358904A1

公开(公告)日：2016-12-08

申请号：US14728053

申请日：2015-06-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Ting Lin ,  Yi-Chun Chen ,  Tien-Hao Tang

IPC: H01L27/02

CPC classification number: H01L27/0274 ,  H01L27/0262 ,  H01L29/0692 ,  H01L29/861

Abstract: An electrostatic discharge (ESD) protection device includes a first trigger element and a first silicon control rectifier (SCR) element. The first trigger element has a first parasitic bipolar junction transistor (BJT) formed in a substrate. The first SCR element has a second parasitic BJT formed in the substrate. The first parasitic BJT and the second parasitic BJT has a common parasitic bipolar base, and the first parasitic BJT has a trigger voltage substantially lower than that of the second parasitic BJT.

Abstract translation: 静电放电（ESD）保护装置包括第一触发元件和第一硅控制整流器（SCR）元件。 第一触发元件具有形成在衬底中的第一寄生双极结型晶体管（BJT）。 第一SCR元件在衬底中形成第二寄生BJT。 第一寄生BJT和第二寄生BJT具有公共寄生双极基极，并且第一寄生BJT的触发电压基本上低于第二寄生BJT的触发电压。

公开(公告)号：US20160204598A1

公开(公告)日：2016-07-14

申请号：US14594173

申请日：2015-01-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Cih Wang ,  Lu-An Chen ,  Tien-Hao Tang

IPC: H02H9/04

CPC classification number: H01L27/0259 ,  H01L27/0255 ,  H01L27/0288 ,  H02H9/046

Abstract: The present invention provides an ESD protection circuit electrically connected between a high voltage power line and a low voltage power line, and the ESD protection circuit includes a bipolar junction transistor (BJT) and a trigger source. A collector of the BJT is electrically connected to the high voltage power line, and an emitter and a base of the BJT are electrically connected to the low voltage power line. The trigger source is electrically connected between the base of the BJT and the high voltage power line.

Abstract translation: 本发明提供一种电连接在高压电力线和低电压电力线之间的ESD保护电路，该ESD保护电路包括双极结型晶体管（BJT）和触发源。 BJT的集电极电连接到高压电力线，并且BJT的发射极和基极电连接到低压电力线。 触发源电连接在BJT的基极和高压电源线之间。

公开(公告)号：US09368484B1

公开(公告)日：2016-06-14

申请号：US14723482

申请日：2015-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chen ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0266 ,  H01L27/0248 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/7851

Abstract: A fin type ESD protection device includes at least one first fin, at least one second fin, and at least one gate structure. The first fin is disposed on a semiconductor substrate, and a source contact contacts the first fin. The second fin is disposed on the semiconductor substrate, and a drain contact contacts the second fin. The first fin and the second fin extend in a first direction respectively, and the first fin is separated from the second fin. The gate structure is disposed between the source contact and the drain contact. The first fin is separated from the drain contact, and the second fin is separated from the source contact.

Abstract translation: 翅片型ESD保护装置包括至少一个第一鳍片，至少一个第二鳍片和至少一个栅极结构。 第一翅片设置在半导体衬底上，源极触点接触第一鳍片。 第二鳍片设置在半导体衬底上，漏极接触件接触第二鳍片。 第一鳍片和第二鳍片分别在第一方向上延伸，并且第一鳍片与第二鳍片分离。 栅极结构设置在源极触点和漏极触点之间。 第一鳍片与漏极接触部分开，第二鳍片与源极接触部分离开。