公开(公告)号：US20150287838A1

公开(公告)日：2015-10-08

申请号：US14742723

申请日：2015-06-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L29/861 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/785 ,  H01L29/861

Abstract: A fin diode structure includes a doped well formed in a substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well isolated from ins of first conductivity type by STIs, at least one doped region of first conductivity type in the substrate between the fins of first conductivity type, the STIs and the doped well and connecting with the fins of first conductivity type, and at least one doped region of second conductivity type in the substrate between the fins of second conductivity type, the STIs and the doped well and connecting with the fins of second conductivity type. The doping concentration of the fins of first conductivity type is greater than that of the doped region of first conductivity type whose doping concentration is greater than that of the doped well of first conductivity type.

Abstract translation: 翅片二极管结构包括在衬底中形成的掺杂阱，第一导电类型的多个鳍和第二导电类型的多个翅片，其通过STI从与第一导电类型的绝缘体隔离的掺杂阱突出，至少一个掺杂区域 第一导电类型的翅片之间的衬底中的第一导电类型，STI和掺杂阱并且与第一导电类型的鳍连接并且在第二导电类型的鳍之间的衬底中的至少一个第二导电类型的掺杂区域 类型，STI和掺杂阱，并与第二导电类型的鳍连接。 第一导电类型的散热片的掺杂浓度大于其掺杂浓度大于第一导电类型的掺杂阱的第一导电类型的掺杂区域的掺杂浓度。

公开(公告)号：US20150123184A1

公开(公告)日：2015-05-07

申请号：US14071670

申请日：2013-11-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Yu-Chun Chen ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/092 ,  H01L27/06 ,  H01L23/60 ,  H01L29/78

CPC classification number: H01L27/0925 ,  H01L21/823892 ,  H01L27/0274 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/785

Abstract: A CMOS device includes a substrate, a pMOS transistor and an nMOS transistor formed on the substrate, and a gated diode. The gated diode includes a floating gate formed on the substrate in between the pMOS transistor and the nMOS transistor and a pair of a p-doped region and an n-doped region formed in the substrate and between the pMOS transistor and the nMOS transistor. The n-doped region is formed between the floating gate and the nMOS transistor, and the p-doped region is formed between the floating gate and the pMOS transistor.

Abstract translation: CMOS器件包括衬底，pMOS晶体管和形成在衬底上的nMOS晶体管，以及门控二极管。 门控二极管包括形成在pMOS晶体管和nMOS晶体管之间的衬底上的浮置栅极和形成在衬底中以及在pMOS晶体管和nMOS晶体管之间的一对p掺杂区域和n掺杂区域。 在浮置栅极和nMOS晶体管之间形成n掺杂区域，并且在浮置栅极和pMOS晶体管之间形成p掺杂区域。

公开(公告)号：US20150054132A1

公开(公告)日：2015-02-26

申请号：US13974939

申请日：2013-08-23

Applicant: United Microelectronics Corp.

Inventor： Chang-Tzu Wang ,  Pei-Shan Tseng ,  Tien-Hao Tang

IPC: H01L29/73 ,  H01L29/66

CPC classification number: H01L29/735 ,  H01L27/0259 ,  H01L29/0821 ,  H01L29/6625 ,  H01L29/861

Abstract: Provided is a lateral BJT including a substrate, a well region, an area, at least one lightly doped region, a first doped region, and a second doped region. The substrate is of a first conductivity type. The well region is of a second conductivity type and is in the substrate. The area is in the well region. The at least one lightly doped region is in the well region below the area. The first doped region and the second doped region are of the first conductivity type and are in the well region on both sides of the area. The first doped region is connected to a cathode. The second doped region is connected to an anode, wherein the doping concentration of the at least one lightly doped region is lower than that of each of the first doped region, the second doped region, and the well region.

Abstract translation: 提供了包括衬底，阱区，区域，至少一个轻掺杂区域，第一掺杂区域和第二掺杂区域的横向BJT。 衬底是第一导电类型。 阱区是第二导电类型并且在衬底中。 该地区在该地区。 该至少一个轻掺杂区域位于该区域下方的阱区域中。 第一掺杂区域和第二掺杂区域是第一导电类型并且在该区域两侧的阱区域中。 第一掺杂区域连接到阴极。 第二掺杂区域连接到阳极，其中至少一个轻掺杂区域的掺杂浓度低于第一掺杂区域，第二掺杂区域和阱区域中的每一个的掺杂浓度。

公开(公告)号：US09455246B2

公开(公告)日：2016-09-27

申请号：US14687921

申请日：2015-04-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L21/70 ,  H01L27/02 ,  H01L29/861 ,  H01L21/76 ,  H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L21/22 ,  H01L21/265 ,  H01L21/306 ,  H01L29/66 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/785 ,  H01L29/861

Abstract: A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.

公开(公告)号：US20150008529A1

公开(公告)日：2015-01-08

申请号：US13937142

申请日：2013-07-08

Applicant: United Microelectronics Corp.

Inventor： Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L27/06

CPC classification number: H01L27/0277

Abstract: Provided is an electrostatic discharge (ESD) protection structure including a substrate, a pick-up region, a first MOS device, a second MOS device, a first doped region and a second doped region. The pick-up region is located in the substrate. The first MOS device has a first drain region of a first conductivity type located in the substrate. The second MOS device has a second drain region of the first conductivity type located in the substrate. The first drain region is closer to the pick up region than the second drain region is. The first doped region of a second conductivity type is located under the first doped region. The second doped region of the second conductivity type is located under the second doped region. The area and/or doping concentration of the first doped region is greater than that of the second doped region.

Abstract translation: 提供一种包括基板，拾取区域，第一MOS器件，第二MOS器件，第一掺杂区域和第二掺杂区域的静电放电（ESD）保护结构。 拾取区域位于基板中。 第一MOS器件具有位于衬底中的第一导电类型的第一漏极区域。 第二MOS器件具有位于衬底中的第一导电类型的第二漏极区域。 第一漏极区域比第二漏极区域更靠近拾取区域。 第二导电类型的第一掺杂区位于第一掺杂区的下方。 第二导电类型的第二掺杂区位于第二掺杂区的下方。 第一掺杂区域的面积和/或掺杂浓度大于第二掺杂区域的面积和/或掺杂浓度。

公开(公告)号：US20140300391A1

公开(公告)日：2014-10-09

申请号：US13858927

申请日：2013-04-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H03K3/013

CPC classification number: H03K19/00 ,  H01L27/0207 ,  H01L27/0738 ,  H01L27/088 ,  H01L27/092 ,  H03K19/00361

Abstract: An output buffer includes an input/output end, a voltage source, a first transistor and a second transistor. The first transistor includes a first end coupled to the input/output end, a second end coupled to the voltage source, and a control end coupled to the voltage source. The second transistor includes a first end coupled to the input/output end, a second end coupled to the voltage source, and a control end coupled to the voltage source. The control end of the first transistor and the control end of the second transistor are substantially perpendicular to each other, and the punch through voltage of the first transistor is higher than the punch through voltage of the second transistor.

Abstract translation: 输出缓冲器包括输入/​​输出端，电压源，第一晶体管和第二晶体管。 第一晶体管包括耦合到输入/输出端的第一端，耦合到电压源的第二端和耦合到电压源的控制端。 第二晶体管包括耦合到输入/输出端的第一端，耦合到电压源的第二端和耦合到电压源的控制端。 第一晶体管的控制端和第二晶体管的控制端基本上彼此垂直，并且第一晶体管的穿通电压高于第二晶体管的穿通电压。

公开(公告)号：US20140057403A1

公开(公告)日：2014-02-27

申请号：US14069179

申请日：2013-10-31

Applicant: United Microelectronics Corp.

Inventor： Chang-Tzu Wang ,  Mei-Ling Chao ,  Chien-Ting Lin

IPC: H01L29/66 ,  H01L21/265

CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/823821 ,  H01L27/0924

Abstract: A method for fabricating a semiconductor device is provided. A fin of a first conductivity type is formed on a substrate of the first conductivity type. A gate is formed on the substrate, wherein the gate covers a portion of the fin. Source and drain regions of a second conductivity type are formed in the fin at respective sides of the gate. A punch-through stopper (PTS) of the first conductivity type is formed in the fin underlying the gate and between the source and drain regions, wherein the PTS has an impurity concentration higher than that of the substrate. A first impurity of the second conductivity type is implanted into the PTS, so as to compensate the impurity concentration of the PTS.

Abstract translation: 提供一种制造半导体器件的方法。 在第一导电类型的衬底上形成第一导电类型的鳍。 栅极形成在衬底上，其中栅极覆盖鳍片的一部分。 第二导电类型的源极和漏极区域形成在栅极的相应侧的翅片中。 第一导电类型的穿通止动件（PTS）形成在栅极下方的栅极和源极和漏极区域之间，其中PTS的杂质浓度高于衬底的杂质浓度。 将第二导电类型的第一杂质注入到PTS中，以补偿PTS的杂质浓度。

公开(公告)号：US09331064B2

公开(公告)日：2016-05-03

申请号：US14742723

申请日：2015-06-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L21/70 ,  H01L27/02 ,  H01L29/861 ,  H01L21/76 ,  H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L21/22 ,  H01L21/265 ,  H01L21/306 ,  H01L29/66 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/785 ,  H01L29/861

Abstract: A fin diode structure includes a doped well formed in a substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well isolated from ins of first conductivity type by STIs, at least one doped region of first conductivity type in the substrate between the fins of first conductivity type, the STIs and the doped well and connecting with the fins of first conductivity type, and at least one doped region of second conductivity type in the substrate between the fins of second conductivity type, the STIs and the doped well and connecting with the fins of second conductivity type. The doping concentration of the fins of first conductivity type is greater than that of the doped region of first conductivity type whose doping concentration is greater than that of the doped well of first conductivity type.

Abstract translation: 翅片二极管结构包括在衬底中形成的掺杂阱，第一导电类型的多个鳍和第二导电类型的多个翅片，其通过STI从与第一导电类型的绝缘体隔离的掺杂阱突出，至少一个掺杂区域 第一导电类型的翅片之间的衬底中的第一导电类型，STI和掺杂阱并且与第一导电类型的鳍连接并且在第二导电类型的鳍之间的衬底中的至少一个第二导电类型的掺杂区域 类型，STI和掺杂阱，并与第二导电类型的鳍连接。 第一导电类型的散热片的掺杂浓度大于其掺杂浓度大于第一导电类型的掺杂阱的第一导电类型的掺杂区域的掺杂浓度。

公开(公告)号：US20150137255A1

公开(公告)日：2015-05-21

申请号：US14082529

申请日：2013-11-18

Applicant: United Microelectronics Corp.

Inventor： Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L27/0277 ,  H01L27/088

Abstract: A semiconductor device is described, including a substrate including a first area and a second area, a first MOS element of a first conductivity type in the first area, and a second MOS element of the first conductivity type in the second area. The first area is closer to a pick-up region of the substrate than the second area. The substrate has a second conductivity type. The bottom depth of a first electrical conduction path in the substrate in the first area is smaller than that of a second electrical conduction path in the substrate in the second area.

Abstract translation: 描述了一种半导体器件，包括包括第一区域和第二区域的衬底，第一区域中的第一导电类型的第一MOS元件和第二区域中的第一导电类型的第二MOS元件。 第一区域比第二区域更靠近基板的拾取区域。 衬底具有第二导电类型。 第一区域中的衬底中的第一导电通路的底部深度小于第二区域中的衬底中的第二导电通路的深度。

公开(公告)号：US08748278B2

公开(公告)日：2014-06-10

申请号：US14069179

申请日：2013-10-31

Applicant: United Microelectronics Corp.

Inventor： Chang-Tzu Wang ,  Mei-Ling Chao ,  Chien-Ting Lin

IPC: H01L21/336

CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/823821 ,  H01L27/0924

Abstract: A method for fabricating a semiconductor device is provided. A fin of a first conductivity type is formed on a substrate of the first conductivity type. A gate is formed on the substrate, wherein the gate covers a portion of the fin. Source and drain regions of a second conductivity type are formed in the fin at respective sides of the gate. A punch-through stopper (PTS) of the first conductivity type is formed in the fin underlying the gate and between the source and drain regions, wherein the PTS has an impurity concentration higher than that of the substrate. A first impurity of the second conductivity type is implanted into the PTS, so as to compensate the impurity concentration of the PTS.

Abstract translation: 提供一种制造半导体器件的方法。 在第一导电类型的衬底上形成第一导电类型的鳍。 栅极形成在衬底上，其中栅极覆盖鳍片的一部分。 第二导电类型的源极和漏极区域形成在栅极的相应侧的翅片中。 第一导电类型的穿通止动件（PTS）形成在栅极下方的栅极和源极和漏极区域之间，其中PTS的杂质浓度高于衬底的杂质浓度。 将第二导电类型的第一杂质注入到PTS中，以补偿PTS的杂质浓度。