公开(公告)号：US10068965B1

公开(公告)日：2018-09-04

申请号：US15718001

申请日：2017-09-28

Applicant: University of Electronic Science and Technology of China

Inventor： Ming Qiao ,  Yang Yu ,  Wentong Zhang ,  Zhengkang Wang ,  Zhenya Zhan ,  Bo Zhang

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/02 ,  H01L29/40 ,  H01L29/739 ,  H01L29/735

Abstract: The present invention relates to a lateral high-voltage device. The device includes a dielectric trench region. A doping-overlapping structure with different doping types alternating mode is provided at least below, on a left side of, or on a right side of the dielectric trench region. The device also includes a dielectric layer, a body field plate, a polysilicon gate, a gate oxide layer, a first N-type heavy doping region, a second N-type heavy doping region, a P-type heavy doping region, a P-well region, the first N-type doping pillar, the second N-type doping pillar, the third N-type doping pillar, the first P-type doping pillar, and the second P-type doping pillar. The invention adopts a dielectric trench region in the drift region to keep the breakdown voltage BV of the device while reducing the surface area of the device, and effectively reducing the device's specific On-Resistance RON,sp.

公开(公告)号：US11888022B2

公开(公告)日：2024-01-30

申请号：US17744779

申请日：2022-05-16

Applicant: University of Electronic Science and Technology of China

Inventor： Wentong Zhang ,  Ning Tang ,  Ke Zhang ,  Nailong He ,  Ming Qiao ,  Zhaoji Li ,  Bo Zhang

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/0607 ,  H01L29/407 ,  H01L29/66325 ,  H01L29/66681 ,  H01L29/7394 ,  H01L29/7823 ,  H01L29/7824

Abstract: An SOI lateral homogenization field high voltage power semiconductor device, and a manufacturing method and application thereof are provided. The device includes a type I conductive semiconductor substrate, a type II conductive drift region, a type I field clamped layer, type I and type II conductive well regions, the first dielectric oxide layer forming a field oxide layer, the second dielectric oxide layer forming a gate oxide layer, a type II conductive buried dielectric layer, a type II conductive source heavily doped region, a type II conductive drain heavily doped region. The first dielectric oxide layer and the floating field plate polysilicon electrodes form a vertical floating field plate distributed throughout the type II conductive drift region to form a vertical floating equipotential field plate array. When the device is in on-state, high doping concentration can be realized by the full-region depletion effect form the vertical field plate arrays.