公开(公告)号：US20230090883A1

公开(公告)日：2023-03-23

申请号：US17752891

申请日：2022-05-25

Applicant: University of Electronic Science and Technology of China

Inventor： Jinping ZHANG ,  Rongrong ZHU ,  Yuanyuan TU ,  Zehong LI ,  Bo ZHANG

IPC: H01L29/06 ,  H01L29/739 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

Abstract: A three-dimensional carrier stored trench IGBT and a manufacturing method thereof are provided. A P-type buried layer and a split gate electrode with equal potential to an emitter metal is introduced on the basis of the traditional carrier stored trench IGBT, which can effectively eliminate the influence of an N-type carrier stored layer on breakdown characteristics of the device through the charge compensation, and at the same time can reduce the on-state voltage drop and improve the trade-off relationship between the on-state voltage drop Vceon and the turn-off loss Eoff. The split gate electrodes is introduced in the Z-axis direction, so that the gate electrodes are distributed at intervals. Therefore, the channel density is reduced. The turning on of the parasitic PMOS has a potential-clamping effect on the NMOS channel, so that the saturation current can be reduced and a wider short-circuit safe operating area (SCSOA) can be obtained.

公开(公告)号：US20230088637A1

公开(公告)日：2023-03-23

申请号：US17752889

申请日：2022-05-25

Applicant: University of Electronic Science and Technology of China

Inventor： Jinping ZHANG ,  Yuanyuan TU ,  Rongrong ZHU ,  Zehong LI ,  Bo ZHANG

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/761 ,  H01L21/765 ,  H01L29/66

Abstract: A split gate carrier stored trench bipolar transistor (CSTBT) with current clamping PMOS include a P-type buried layer and a split gate electrode with equal potential to an emitter metal on the basis of the traditional CSTBT, which effectively eliminates the influence of an N-type carrier stored layer on breakdown characteristics of the device through the charge compensation effect, and helps to improve the trade-off relationship between the on-state voltage drop and the turn-off loss. Moreover, the introduction of a parasitic PMOS structure can reduce the saturation current and improve short-circuit safe operating area of the device, reduce the Miller capacitance, and improve the switching speed of the device and reduce the switching loss of the device. In addition, the split gate CSTBT integrating the split gate electrode and gate electrode in the same trench can shorten the distance between PMOS and NMOS channels.