公开(公告)号：US20180026129A1

公开(公告)日：2018-01-25

申请号：US15602122

申请日：2017-05-23

Applicant: University of Electronic Science and Technology of China

Inventor： Min REN ,  Chi XIE ,  Jiaju LI ,  Ziqi ZHONG ,  Zehong LI ,  Jinping ZHANG ,  Wei GAO ,  Bo ZHANG

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/7811 ,  H01L21/30604 ,  H01L29/0611 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0661 ,  H01L29/0684 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/405 ,  H01L29/407 ,  H01L29/41741

Abstract: Edge termination structures for power semiconductor devices (or power devices) are disclosed. The purpose of this invention is to reduce the difficulty of deep trench etching and dielectric filling by adopting an inverted trapezoidal trench. In order to save the area of edge termination and get a high blocking voltage on condition that the angle between the sidewall of the trench and horizontal is large, fixed charges are introduced at a particular location in the trench. Due to the Coulomb interaction between the ionized impurity in the drift region and the fixed charges, the depletion region of the terminal PN junction can extend fully, which relieves the concentration of electric field there. Therefore, the edge termination can exhibit a high breakdown voltage near to that of the parallel plane junction with a smaller area and the reduced technical difficulty of deep trench etching and dielectric filling.

公开(公告)号：US20160315142A1

公开(公告)日：2016-10-27

申请号：US15197701

申请日：2016-06-29

Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA ,  ELECTRONIC AND INFORMATION ENGINEERING IN DONGGUAN , UESTC

Inventor： Zehong LI ,  Wenlong SONG ,  Xunyi SONG ,  Hongming GU ,  Youbiao ZOU ,  Jinping ZHANG ,  Bo ZHANG

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/0634 ,  H01L21/263 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802

Abstract: A method for manufacturing a vertical super junction drift layer of a power semiconductor device. The method includes: a): adopting P+ single crystal silicon to prepare a P+ substrate; b): finishing top processes of the devices on the P+ substrate, forming at least P type region, manufacturing active area and metallizing the top surface of the P+ substrate; c): thinning the back surface of the P+ single crystal silicon; d): selectively implanting H+ ions at the back surface repeatedly and then annealing to form N pillars in the P type region; and e): metallizing the back surface.

Abstract translation: 一种用于制造功率半导体器件的垂直超结漂移层的方法。 该方法包括：a）：采用P +单晶硅制备P +底物; b）：完成P +衬底上的器件的顶部工艺，至少形成P型区域，制造有源面积并金属化P +衬底的顶表面; c）：使P +单晶硅的背面变薄; d）：重复地在背面注入H +离子，然后退火以在P型区域中形成N柱; 和e）：金属化背面。

公开(公告)号：US20180026143A1

公开(公告)日：2018-01-25

申请号：US15602107

申请日：2017-05-23

Applicant: University of Electronic Science and Technology of China

Inventor： Min REN ,  Yuci LIN ,  Huiping BAO ,  Lei LUO ,  Zehong LI ,  Bo ZHANG

IPC: H01L29/872 ,  H01L29/66 ,  H01L29/15

CPC classification number: H01L29/872 ,  H01L21/26586 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/157 ,  H01L29/158 ,  H01L29/1608 ,  H01L29/66143

Abstract: The present invention relates to the field of semiconductor technology, particularly to a super-junction schottky diode. According to the present invention, the effective area of schottky junction is increased by forming the schottky junction in the trench located in the body of the device. Therefore, the current capacity of this novel schottky diode can be greatly improved. In addition, a super-junction structure is used to improve the device's reverse breakdown voltage and reduce the reverse leakage current. The super-junction schottky diode provided in the present invention can achieve a larger forward current, a lower on-resistance and a better reverse breakdown characteristic.

公开(公告)号：US20170084728A1

公开(公告)日：2017-03-23

申请号：US15372352

申请日：2016-12-07

Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA ,  INSTITUTE OF ELECTRONIC AND INFORMATION ENGINEERING IN DONGGUAN, UESTC

Inventor： Jinping ZHANG ,  Zehong LI ,  Jingxiu LIU ,  Min REN ,  Bo ZHANG ,  Zhaoji LI

IPC: H01L29/74 ,  H01L29/10 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/265 ,  H01L29/747 ,  H01L29/40

CPC classification number: H01L29/7424 ,  H01L21/02233 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66325 ,  H01L29/66386 ,  H01L29/7394 ,  H01L29/747 ,  H01L29/78

Abstract: A bidirectional Metal-Oxide-Semiconductor (MOS) device, including a P-type substrate, and an active region. The active region includes a drift region, a first MOS structure and a second MOS structure; the first MOS structure includes a first P-type body region, a first P+ contact region, a first N+ source region, a first metal electrode, and a first gate structure; the second MOS structure includes a second P-type body region, a second P+ contact region, a second N+ source region, a second metal electrode, and a second gate structure; and the drift region includes a dielectric slot, a first N-type layer, a second N-type layer, and an N-type region. The active region is disposed on the upper surface of the P-type substrate. The first MOS structure and the second MOS structure are symmetrically disposed on two ends of the upper layer of the drift region.

公开(公告)号：US20200235231A1

公开(公告)日：2020-07-23

申请号：US16601609

申请日：2019-10-15

Applicant: University of Electronic Science and Technology of China

Inventor： Zehong LI ,  Xin PENG ,  Yishang ZHAO ,  Min REN ,  Bo ZHANG

IPC: H01L29/739 ,  H01L29/423 ,  H01L29/10

Abstract: The present invention relates to the technical field of power semiconductor devices, particularly to an insulated gate bipolar transistor with a MOS controllable hole path. According to the present invention, a MOS controllable gate structure formed by a gate dielectric layer, a MOS control gate electrode and a P-type MOS channel region are embedded in a P+ floating p-body region of the conventional IGBT structure. The MOS region is equivalent to a switch controlled by a gate voltage. When the device is turned on under a forward voltage, the potential of the p-body region is floated to store holes, reducing the saturation conduction voltage drop of the device. Under the condition of turn-off and short-circuit, the hole extracting path is provided and the Miller capacitance is lowered, thereby lowering the turn-off losses and enhancing the short-circuit withstand capability.

公开(公告)号：US20190371937A1

公开(公告)日：2019-12-05

申请号：US15774291

申请日：2016-09-17

Applicant: University of Electronic Science and Technology of China

Inventor： Min REN ,  Yuci LIN ,  Chi XIE ,  Zhiheng SU ,  Zehong LI ,  Jinping ZHANG ,  Wei GAO ,  Bo ZHANG

IPC: H01L29/78 ,  H01L29/423

Abstract: A trench MOS device with improved single event burnout endurance, applied in the field of semiconductor. The device is provided, in an epitaxial layer, with a conductive type semiconductor pillar connected to a source and a second conductive type current-directing region. Whereby. the trajectory of the electron-hole pairs induced by the single event effect is changed and thus avoids the single event burnout caused by the triggering of parasitic transistors, therefore improving the endurance of the single event burnout of the trench MOS device.

公开(公告)号：US20190067415A1

公开(公告)日：2019-02-28

申请号：US15774286

申请日：2016-09-17

Applicant: University of Electronic Science and Technology of China

Inventor： Min REN ,  Yumeng ZHANG ,  Cong DI ,  Jingzhi XIONG ,  Zehong LI ,  Jinping ZHANG ,  Wei GAO ,  Bo ZHANG

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/0615 ,  H01L29/0638 ,  H01L29/407 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7823

Abstract: A junction termination with an internal field plate, the field plate structure and the junction termination extension region are folded inside the device to make full use of the thickness of the drift region in the body, thereby reducing the area of the termination and relieving the electric field concentration at the end of the PN junction. The breakdown position is transferred from the surface into the body of the original PN junction, and the withstand voltage of termination can reach to the breakdown voltage of the parallel plane junction. Under such design, a smaller area can be obtained than that of the conventional structure at the same withstand voltage.

公开(公告)号：US20230090883A1

公开(公告)日：2023-03-23

申请号：US17752891

申请日：2022-05-25

Applicant: University of Electronic Science and Technology of China

Inventor： Jinping ZHANG ,  Rongrong ZHU ,  Yuanyuan TU ,  Zehong LI ,  Bo ZHANG

IPC: H01L29/06 ,  H01L29/739 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

Abstract: A three-dimensional carrier stored trench IGBT and a manufacturing method thereof are provided. A P-type buried layer and a split gate electrode with equal potential to an emitter metal is introduced on the basis of the traditional carrier stored trench IGBT, which can effectively eliminate the influence of an N-type carrier stored layer on breakdown characteristics of the device through the charge compensation, and at the same time can reduce the on-state voltage drop and improve the trade-off relationship between the on-state voltage drop Vceon and the turn-off loss Eoff. The split gate electrodes is introduced in the Z-axis direction, so that the gate electrodes are distributed at intervals. Therefore, the channel density is reduced. The turning on of the parasitic PMOS has a potential-clamping effect on the NMOS channel, so that the saturation current can be reduced and a wider short-circuit safe operating area (SCSOA) can be obtained.

公开(公告)号：US20230088637A1

公开(公告)日：2023-03-23

申请号：US17752889

申请日：2022-05-25

Applicant: University of Electronic Science and Technology of China

Inventor： Jinping ZHANG ,  Yuanyuan TU ,  Rongrong ZHU ,  Zehong LI ,  Bo ZHANG

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/761 ,  H01L21/765 ,  H01L29/66

Abstract: A split gate carrier stored trench bipolar transistor (CSTBT) with current clamping PMOS include a P-type buried layer and a split gate electrode with equal potential to an emitter metal on the basis of the traditional CSTBT, which effectively eliminates the influence of an N-type carrier stored layer on breakdown characteristics of the device through the charge compensation effect, and helps to improve the trade-off relationship between the on-state voltage drop and the turn-off loss. Moreover, the introduction of a parasitic PMOS structure can reduce the saturation current and improve short-circuit safe operating area of the device, reduce the Miller capacitance, and improve the switching speed of the device and reduce the switching loss of the device. In addition, the split gate CSTBT integrating the split gate electrode and gate electrode in the same trench can shorten the distance between PMOS and NMOS channels.

公开(公告)号：US20160322483A1

公开(公告)日：2016-11-03

申请号：US15209745

申请日：2016-07-13

Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA ,  INSTITUTE OF ELECTRONIC AND INFORMATION ENGINEERING IN DONGGUAN, UESTC

Inventor： Jinping ZHANG ,  Yadong SHAN ,  Gaochao XU ,  Xin YAO ,  Jingxiu LIU ,  Zehong LI ,  Min REN ,  Bo ZHANG

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7397 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/4236

Abstract: A bidirectional IGBT device, including a cellular structure including: two MOS structures, a substrate drift layer, two highly doped buried layers operating for carrier storage or field stop, two metal electrodes, and isolating dielectrics. Each MOS structure includes: a body region, a heavily doped source region, a body contact region, and a gate structure. Each gate structure includes: a gate dielectric and a gate conductive material. The two MOS structures are symmetrically disposed on the top surface and the back surface of the substrate drift layer. The heavily doped source region and the body contact region are disposed in the body region and independent from each other, and both surfaces of the heavily doped source region and the body contact region are connected to each of the two metal electrodes. The gate dielectric separates the gate conductive material from a channel region of each of the MOS structures.

Abstract translation: 一种双向IGBT器件，其包括：两个MOS结构，衬底漂移层，用于载流子存储或场停止的两个高掺杂掩埋层，两个金属电极和隔离电介质。 每个MOS结构包括：体区，重掺杂源区，体接触区和栅结构。 每个栅极结构包括：栅极电介质和栅极导电材料。 两个MOS结构对称地设置在衬底漂移层的顶表面和背表面上。 重掺杂源极区域和体接触区域设置在体区域中并且彼此独立，并且重掺杂源极区域和体接触区域的两个表面连接到两个金属电极中的每一个。 栅极电介质将栅极导电材料与每​​个MOS结构的沟道区分离。