公开(公告)号：US20130311756A1

公开(公告)日：2013-11-21

申请号：US13947958

申请日：2013-07-22

申请人： VINODH GOPAL ,  JAMES D. GULILFORD ,  GILBERT M. WOLRICH ,  WAIDI K. FEGHALI ,  ERDINC OZTURK ,  MARTIN G. DIXON ,  SEAN P. MIRKES ,  BRET L. TOLL ,  MAXIM LOKTYUKHIN ,  MARK C. DAVIS ,  ALEXANDRE J. FARCY

发明人： VINODH GOPAL ,  JAMES D. GULILFORD ,  GILBERT M. WOLRICH ,  WAIDI K. FEGHALI ,  ERDINC OZTURK ,  MARTIN G. DIXON ,  SEAN P. MIRKES ,  BRET L. TOLL ,  MAXIM LOKTYUKHIN ,  MARK C. DAVIS ,  ALEXANDRE J. FARCY

IPC分类号： G06F9/30

CPC分类号： G06F9/30032 ,  G06F9/30094 ,  G06F9/30098

摘要： A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

摘要翻译： 一个方面的方法可以包括接收旋转指令。 旋转指令可以指示源操作数和旋转量。 结果可以存储在由旋转指令指示的目标操作数中。 结果可能使源操作数旋转了旋转量。 旋转指令的执行可以在不读取进位标志的情况下完成。

公开(公告)号：US20140006536A1

公开(公告)日：2014-01-02

申请号：US13538826

申请日：2012-06-29

申请人： JAMES D. GUILFORD ,  VINODH GOPAL ,  GILBERT M. WOLRICH ,  ERDINC OZTURK ,  WAJDI K. FEGHALI

发明人： JAMES D. GUILFORD ,  VINODH GOPAL ,  GILBERT M. WOLRICH ,  ERDINC OZTURK ,  WAJDI K. FEGHALI

IPC分类号： G06F15/16 ,  G06F15/167

CPC分类号： H03M7/60 ,  G06F9/30029 ,  H03M7/3068 ,  H03M7/6058

摘要： An embodiment may include circuitry that may be capable of performing compression-related operations that may include: (a) indicating, at least in part, in a data structure at least one position of at least one subset of characters that are to be encoded as a symbol, (b) comparing, at least in part, at least one pair of multi-byte data words that are of identical predetermined fixed size, (c) maintaining, at least in part, an array of pointers to potentially matching strings that are to be compared with at least one currently examined string, and/or (d) allocating, at least in part, a first buffer portion to store at least one portion of uncompressed data from an application buffer that is to be input for compression to produce a compressed data stream. Other embodiments are described and claimed.

摘要翻译： 实施例可以包括可以执行压缩相关操作的电路，其可以包括：（a）至少部分地在数据结构中指示要被编码为的至少一个字符子集的至少一个位置 （b）至少部分比较至少一对具有相同预定固定大小的多字节数据字，（c）至少部分维持指向潜在匹配字符串的指针数组， 与至少一个当前检查的字符串进行比较，和/或（d）至少部分地分配第一缓冲器部分，以将来自要输入的压缩数据的至少一部分未压缩数据存储到要压缩的应用缓冲器中 产生压缩数据流。 描述和要求保护其他实施例。

公开(公告)号：US20150347231A1

公开(公告)日：2015-12-03

申请号：US14293791

申请日：2014-06-02

申请人： VINODH GOPAL ,  ERDINC OZTURK

发明人： VINODH GOPAL ,  ERDINC OZTURK

IPC分类号： G06F11/10 ,  H03M13/15

CPC分类号： G06F11/1088 ,  G06F2211/1057 ,  H03M13/1515 ,  H03M13/159 ,  H03M13/373

摘要： Erasure code syndrome computation based on Reed Solomon (RS) operations in a Galois field to permit reconstruction of data of more than 2 failed storage units. Syndrome computation may be performed with coefficient exponents that consist of −1, 0, and 1. A product xD of a syndrome is computed as a left-shift of data byte D, and selective compensation based on the most significant bit of D. A product x−1D of a syndrome is computed as a right-shift of data byte D, and selective compensation based on the most significant bit of D. Compensation may include bit-wise XORing shift results with a constant derived from an irreducible polynomial associated with the Galois field. A set of erasure code syndromes may be computed for each of multiple nested arrays of independent storage units. Data reconstruction includes solving coefficients of the syndromes as a Vandermonde matrix.

摘要翻译： 基于Galois域中的Reed Solomon（RS）操作的擦除码校验子计算，以允许重建超过2个故障存储单元的数据。 综合征计算可以用由-1，0和1组成的系数指数来执行。综合征的乘积xD被计算为数据字节D的左移，并且基于D的最高有效位的选择性补偿。 综合征的乘积x-1D被计算为数据字节D的右移，并且基于D的最高有效位的选择性补偿。补偿可以包括具有从与不相关的多项式相关联的不可约多项式得到的常数的逐位异或移位结果 伽罗瓦领域。 可以为独立存储单元的多个嵌套阵列中的每一个计算一组擦除代码综合征。 数据重建包括求解综合征的系数作为Vandermonde矩阵。

公开(公告)号：US20140019725A1

公开(公告)日：2014-01-16

申请号：US13707105

申请日：2012-12-06

申请人： ERDINC OZTURK ,  VINODH GOPAL ,  JAMES GUILFORD

发明人： ERDINC OZTURK ,  VINODH GOPAL ,  JAMES GUILFORD

IPC分类号： G06F9/30

CPC分类号： G06F9/3001 ,  G06F7/52 ,  G06F7/523 ,  G06F7/544 ,  G06F9/30036 ,  G06F2207/5523

摘要： Methods, systems, and apparatuses are disclosed for implementing fast large-integer arithmetic within an integrated circuit, such as on IA (Intel Architecture) processors, in which such means include receiving a 512-bit value for squaring, the 512-bit value having eight sub-elements each of 64-bits and performing a 512-bit squaring algorithm by: (i) multiplying every one of the eight sub-elements by itself to yield a square of each of the eight sub-elements, the eight squared sub-elements collectively identified as T1, (ii) multiplying every one of the eight sub-elements by the other remaining seven of the eight sub-elements to yield an asymmetric intermediate result having seven diagonals therein, wherein each of the seven diagonals are of a different length, (iii) reorganizing the asymmetric intermediate result having the seven diagonals therein into a symmetric intermediate result having four diagonals each of 7×1 sub-elements of the 64-bits in length arranged across a plurality of columns, (iv) adding all sub-elements within their respective columns, the added sub-elements collectively identified as T2, and (v) yielding a final 512-bit squared result of the 512-bit value by adding the value of T2 twice with the value of T1 once. Other related embodiments are disclosed.

摘要翻译： 公开了用于在诸如IA（Intel Architecture）处理器之类的集成电路内实现快速大整数运算的方法，系统和装置，其中这种装置包括接收512位的平方值，512位值具有 八个子元素，每个64位，并通过以下方式执行512位平方算法：（i）将八个子元素中的每一个本身相乘以产生八个子元素中的每一个的平方，八个子元素 - 集体标识为T1的元件，（ii）将八个子元素中的每一个乘以八个子元素中的其余七个子元素以产生其中具有七个对角线的不对称中间结果，其中七个对角线中的每一个为 （iii）将其中具有七个对角线的非对称中间结果重新组合成具有四个对角线的对称中间结果，每个对角线的长度为64位的7×1个子元素排列成跨越多个 列，（iv）将其所有列中的所有子元素加入集体标识为T2的所添加的子元素，以及（v）通过将T2值增加两次来产生512位值的最终512位平方结果 其T1值一次。 公开了其他相关实施例。