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    TECHNIQUES TO ACCELERATE LOSSLESS COMPRESSION
    2.
    发明申请
    TECHNIQUES TO ACCELERATE LOSSLESS COMPRESSION 审中-公开
    加快无损压缩的技术

    公开(公告)号：US20140006536A1

    公开(公告)日：2014-01-02

    申请号：US13538826

    申请日：2012-06-29

    申请人： JAMES D. GUILFORD ,  VINODH GOPAL ,  GILBERT M. WOLRICH ,  ERDINC OZTURK ,  WAJDI K. FEGHALI

    发明人： JAMES D. GUILFORD ,  VINODH GOPAL ,  GILBERT M. WOLRICH ,  ERDINC OZTURK ,  WAJDI K. FEGHALI

    IPC分类号： G06F15/16 ,  G06F15/167

    CPC分类号： H03M7/60 ,  G06F9/30029 ,  H03M7/3068 ,  H03M7/6058

    摘要： An embodiment may include circuitry that may be capable of performing compression-related operations that may include: (a) indicating, at least in part, in a data structure at least one position of at least one subset of characters that are to be encoded as a symbol, (b) comparing, at least in part, at least one pair of multi-byte data words that are of identical predetermined fixed size, (c) maintaining, at least in part, an array of pointers to potentially matching strings that are to be compared with at least one currently examined string, and/or (d) allocating, at least in part, a first buffer portion to store at least one portion of uncompressed data from an application buffer that is to be input for compression to produce a compressed data stream. Other embodiments are described and claimed.

    摘要翻译： 实施例可以包括可以执行压缩相关操作的电路，其可以包括：（a）至少部分地在数据结构中指示要被编码为的至少一个字符子集的至少一个位置 （b）至少部分比较至少一对具有相同预定固定大小的多字节数据字，（c）至少部分维持指向潜在匹配字符串的指针数组， 与至少一个当前检查的字符串进行比较，和/或（d）至少部分地分配第一缓冲器部分，以将来自要输入的压缩数据的至少一部分未压缩数据存储到要压缩的应用缓冲器中 产生压缩数据流。 描述和要求保护其他实施例。

    TECHNIQUES TO EFFICIENTLY COMPUTE ERASURE CODES HAVING POSITIVE AND NEGATIVE COEFFICIENT EXPONENTS TO PERMIT DATA RECOVERY FROM MORE THAN TWO FAILED STORAGE UNITS
    3.
    发明申请
    TECHNIQUES TO EFFICIENTLY COMPUTE ERASURE CODES HAVING POSITIVE AND NEGATIVE COEFFICIENT EXPONENTS TO PERMIT DATA RECOVERY FROM MORE THAN TWO FAILED STORAGE UNITS 有权
    有效地计算具有积极和负面的系统性能的有效代码的技术，允许数据恢复超过两个失败的存储单元

    公开(公告)号：US20150347231A1

    公开(公告)日：2015-12-03

    申请号：US14293791

    申请日：2014-06-02

    申请人： VINODH GOPAL ,  ERDINC OZTURK

    发明人： VINODH GOPAL ,  ERDINC OZTURK

    IPC分类号： G06F11/10 ,  H03M13/15

    CPC分类号： G06F11/1088 ,  G06F2211/1057 ,  H03M13/1515 ,  H03M13/159 ,  H03M13/373

    摘要： Erasure code syndrome computation based on Reed Solomon (RS) operations in a Galois field to permit reconstruction of data of more than 2 failed storage units. Syndrome computation may be performed with coefficient exponents that consist of −1, 0, and 1. A product xD of a syndrome is computed as a left-shift of data byte D, and selective compensation based on the most significant bit of D. A product x−1D of a syndrome is computed as a right-shift of data byte D, and selective compensation based on the most significant bit of D. Compensation may include bit-wise XORing shift results with a constant derived from an irreducible polynomial associated with the Galois field. A set of erasure code syndromes may be computed for each of multiple nested arrays of independent storage units. Data reconstruction includes solving coefficients of the syndromes as a Vandermonde matrix.

    摘要翻译： 基于Galois域中的Reed Solomon（RS）操作的擦除码校验子计算，以允许重建超过2个故障存储单元的数据。 综合征计算可以用由-1，0和1组成的系数指数来执行。综合征的乘积xD被计算为数据字节D的左移，并且基于D的最高有效位的选择性补偿。 综合征的乘积x-1D被计算为数据字节D的右移，并且基于D的最高有效位的选择性补偿。补偿可以包括具有从与不相关的多项式相关联的不可约多项式得到的常数的逐位异或移位结果 伽罗瓦领域。 可以为独立存储单元的多个嵌套阵列中的每一个计算一组擦除代码综合征。 数据重建包括求解综合征的系数作为Vandermonde矩阵。

    METHOD FOR FAST LARGE-INTEGER ARITHMETIC ON IA PROCESSORS
    4.
    发明申请
    METHOD FOR FAST LARGE-INTEGER ARITHMETIC ON IA PROCESSORS 有权
    用于IA处理器的快速大整数算术的方法

    公开(公告)号：US20140019725A1

    公开(公告)日：2014-01-16

    申请号：US13707105

    申请日：2012-12-06

    申请人： ERDINC OZTURK ,  VINODH GOPAL ,  JAMES GUILFORD

    发明人： ERDINC OZTURK ,  VINODH GOPAL ,  JAMES GUILFORD

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3001 ,  G06F7/52 ,  G06F7/523 ,  G06F7/544 ,  G06F9/30036 ,  G06F2207/5523

    摘要： Methods, systems, and apparatuses are disclosed for implementing fast large-integer arithmetic within an integrated circuit, such as on IA (Intel Architecture) processors, in which such means include receiving a 512-bit value for squaring, the 512-bit value having eight sub-elements each of 64-bits and performing a 512-bit squaring algorithm by: (i) multiplying every one of the eight sub-elements by itself to yield a square of each of the eight sub-elements, the eight squared sub-elements collectively identified as T1, (ii) multiplying every one of the eight sub-elements by the other remaining seven of the eight sub-elements to yield an asymmetric intermediate result having seven diagonals therein, wherein each of the seven diagonals are of a different length, (iii) reorganizing the asymmetric intermediate result having the seven diagonals therein into a symmetric intermediate result having four diagonals each of 7×1 sub-elements of the 64-bits in length arranged across a plurality of columns, (iv) adding all sub-elements within their respective columns, the added sub-elements collectively identified as T2, and (v) yielding a final 512-bit squared result of the 512-bit value by adding the value of T2 twice with the value of T1 once. Other related embodiments are disclosed.

    摘要翻译： 公开了用于在诸如IA（Intel Architecture）处理器之类的集成电路内实现快速大整数运算的方法，系统和装置，其中这种装置包括接收512位的平方值，512位值具有 八个子元素，每个64位，并通过以下方式执行512位平方算法：（i）将八个子元素中的每一个本身相乘以产生八个子元素中的每一个的平方，八个子元素 - 集体标识为T1的元件，（ii）将八个子元素中的每一个乘以八个子元素中的其余七个子元素以产生其中具有七个对角线的不对称中间结果，其中七个对角线中的每一个为 （iii）将其中具有七个对角线的非对称中间结果重新组合成具有四个对角线的对称中间结果，每个对角线的长度为64位的7×1个子元素排列成跨越多个 列，（iv）将其所有列中的所有子元素加入集体标识为T2的所添加的子元素，以及（v）通过将T2值增加两次来产生512位值的最终512位平方结果 其T1值一次。 公开了其他相关实施例。

    HYBRID CAM ASSISTED DEFLATE DECOMPRESSION ACCELERATOR
    7.
    发明申请
    HYBRID CAM ASSISTED DEFLATE DECOMPRESSION ACCELERATOR 有权
    混合辅助辅助解码加速器

    公开(公告)号：US20150381202A1

    公开(公告)日：2015-12-31

    申请号：US14317698

    申请日：2014-06-27

    申请人： SUDHIR K. SATPATHY ,  SANU K. MATHEW ,  VINODH GOPAL ,  RAM K. KRISHNAMURTHY

    发明人： SUDHIR K. SATPATHY ,  SANU K. MATHEW ,  VINODH GOPAL ,  RAM K. KRISHNAMURTHY

    IPC分类号： H03M7/42 ,  G06F12/06

    CPC分类号： G06F12/0646 ,  G06F2212/1021 ,  G06F2212/401 ,  G11C15/00 ,  G11C15/04 ,  H03M7/3059 ,  H03M7/3084 ,  H03M7/3086 ,  H03M7/40

    摘要： Disclosed is an integrated circuit including a memory device including a first portion and a second portion. The first portion is a first type of content addressable memory (CAM) with a first set of cells and the second portion is a second type of CAM with a second set of cells. The first set of cells is smaller than the second set of cells. The integrated circuit further includes a decompression accelerator coupled to the memory device, the decompression accelerator to generate a plurality of length codes. Each of the plurality of length codes include at least one bit. The plurality of length codes are generated using a symbol received from an encoded data stream that includes a plurality of symbols. The decompression accelerator further to store the plurality of length codes in the first portion of the memory device in an order according to their respective number of bits.

    摘要翻译： 公开了一种集成电路，其包括包括第一部分和第二部分的存储器件。 第一部分是具有第一组单元的第一类型的内容可寻址存储器（CAM），并且第二部分是具有第二组单元格的第二类型的CAM。 第一组单元格小于第二组单元格。 集成电路还包括耦合到存储器件的解压加速器，解压加速器以产生多个长度代码。 多个长度码中的每一个包括至少一个位。 使用从包括多个符号的编码数据流接收的符号来生成多个长度码。 所述解压缩加速器进一步按照它们各自的位数按顺序将所述多个长度代码存储在所述存储器件的第一部分中。

    FILTER FOR NETWORK INTRUSION AND VIRUS DETECTION
    9.
    发明申请
    FILTER FOR NETWORK INTRUSION AND VIRUS DETECTION 有权
    用于网络入侵和病毒检测的过滤器

    公开(公告)号：US20100169401A1

    公开(公告)日：2010-07-01

    申请号：US12346734

    申请日：2008-12-30

    申请人： VINODH GOPAL ,  Christopher F. Clark ,  Gilbert Wolrich ,  Wajdi Feghali

    发明人： VINODH GOPAL ,  Christopher F. Clark ,  Gilbert Wolrich ,  Wajdi Feghali

    IPC分类号： G06F17/10

    CPC分类号： H04L63/145 ,  G06F7/02 ,  G06F17/30949 ,  G06F17/30985 ,  G06F21/567 ,  G06F2207/025 ,  H04L63/0245 ,  H04L63/1416

    摘要： Methods and apparatus to perform string matching for network packet inspection are disclosed. In some embodiments there is a set of string matching slice circuits, each slice circuit of the set being configured to perform string matching steps in parallel with other slice circuits. Each slice circuit may include an input window storing some number of bytes of data from an input data steam. The input window of data may be padded if necessary, and then multiplied by a polynomial modulo an irreducible Galois-field polynomial to generate a hash index. A storage location of a memory corresponding to the hash index may be accessed to generate a slice-hit signal of a set of H slice-hit signals. The slice-hit signal may be provided to an AND-OR logic array where the set of H slice-hit signals is logically combined into a match result.

    摘要翻译： 公开了对网络包检测进行字符串匹配的方法和装置。 在一些实施例中，存在一组字符串匹配限幅电路，该组的每个片电路被配置为与其他片电路并行地执行字符串匹配步骤。 每个切片电路可以包括从输入数据蒸汽存储一些数量的数据字节的输入窗口。 如果需要，可以填充数据的输入窗口，然后乘以多项式模数不可约伽罗瓦域多项式以生成散列索引。 可以访问与散列索引相对应的存储器的存储位置，以产生一组H个切片命中信号的切片命中信号。 切片命中信号可以被提供给AND逻辑阵列，其中H组切片命中信号的组合被逻辑地组合成匹配​​结果。

    HARDWARE ACCELERATORS AND METHODS FOR HIGH-PERFORMANCE AUTHENTICATED ENCRYPTION
    10.
    发明申请
    HARDWARE ACCELERATORS AND METHODS FOR HIGH-PERFORMANCE AUTHENTICATED ENCRYPTION 审中-公开

    公开(公告)号：US20190042249A1

    公开(公告)日：2019-02-07

    申请号：US15943654

    申请日：2018-04-02

    申请人： VIKRAM SURESH ,  SANU MATHEW ,  SUDHIR SATPATHY ,  VINODH GOPAL

    发明人： VIKRAM SURESH ,  SANU MATHEW ,  SUDHIR SATPATHY ,  VINODH GOPAL

    IPC分类号： G06F9/30 ,  G06F9/38 ,  H04L9/06

    摘要： Methods and apparatuses relating to high-performance authenticated encryption are described. A hardware accelerator may include a vector register to store an input vector of a round of an encryption operation; a circuit including a first data path including a first modular adder coupled to a first input from the vector register and a second input from the vector register, and a second modular adder coupled to the first modular adder and a second data path from the vector register, and the second data path including a first logical XOR circuit coupled to the second input and a third data path from the vector register, a first rotate circuit coupled to the first logical XOR circuit, a second logical XOR circuit coupled to the first rotate circuit and the third data path, and a second rotate circuit coupled to the second logical XOR circuit; and a control circuit to cause the first modular adder and the second modular adder of the first data path and the first logical XOR circuit, the second logical XOR circuit, the first rotate circuit, and the second rotate circuit of the second data path to perform a portion of the round according to one or more control values, and store a first result from the first data path for the portion and a second result from the second data path for the portion into the vector register.