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公开(公告)号：US20080298246A1
公开(公告)日：2008-12-04
申请号：US11756984
申请日：2007-06-01
申请人： William A. Hughes , Chen-Ping Yang
发明人： William A. Hughes , Chen-Ping Yang
CPC分类号： H04L45/00 , H04L47/10 , H04L47/125 , H04L49/3009
摘要： In one embodiment, a node comprises a plurality of interface circuits coupled to a node controller. Each of the plurality of interface circuits is configured to couple to a respective link of a plurality of links. The node controller is configured to select a first link from two or more of the plurality of links to transmit a first packet, wherein the first link is selected responsive to a relative amount of traffic transmitted via each of the two or more of the plurality of links.
摘要翻译： 在一个实施例中，节点包括耦合到节点控制器的多个接口电路。 多个接口电路中的每一个被配置为耦合到多个链路的相应链路。 所述节点控制器被配置为从所述多个链路中的两个或更多个链路中选择第一链路以发送第一分组，其中响应于经由所述多个分组中的两个或更多个中的每一个发送的相对通信量来选择所述第一链路 链接。
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公开(公告)号：US20080148135A1
公开(公告)日：2008-06-19
申请号：US11610219
申请日：2006-12-13
IPC分类号： G06F11/07
CPC分类号： H04L1/0061 , H04L1/0079 , H04L1/1829 , H04L2001/0097
摘要： In an embodiment, a node comprises a packet scheduler configured to schedule a packet to be transmitted on the link, the packet comprising a command and associated packet data. Coupled to the packet scheduler and configured to transmit the packet on the link, and interface circuit is configured to generate error detection data covering the packet. The interface circuit is configured to transmit the error detection data covering the packet at an end of the packet, and is further configured to insert at least one partial error detection data within the packet. The partial error detection data covers a portion of the packet that precedes the partial error detection data. A receiver is configured to receive the data and forward the data based on partial CRC check.
摘要翻译： 在一个实施例中，节点包括分组调度器，其被配置为调度要在链路上发送的分组，所述分组包括命令和相关联的分组数据。 耦合到分组调度器并且被配置为在链路上传送分组，并且接口电路被配置为生成覆盖分组的错误检测数据。 接口电路被配置为在分组的末尾发送覆盖分组的错误检测数据，并且还被配置为在分组内插入至少一个部分错误检测数据。 部分错误检测数据覆盖部分错误检测数据之前的分组的一部分。 接收机被配置为接收数据并基于部分CRC校验转发数据。
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公开(公告)号：USRE44487E1
公开(公告)日：2013-09-10
申请号：US13240272
申请日：2011-09-22
CPC分类号： H04L1/0011 , H04L1/0007 , H04L1/0061 , H04L1/18
摘要： In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.
摘要翻译： 在一个实施例中，节点包括分组调度器，其被配置为调度要在链路上传送的分组以及耦合到分组调度器并被配置为在链路上传送分组的接口电路。 接口电路被配置为生成覆盖分组的错误检测数据，其中在链路上的分组之间传送错误检测数据。 接口电路被配置为通过一次错误检测数据的传输来覆盖多达N个分组，其中N是> = 2的整数。 由一个错误检测数据传输覆盖的分组的数量由接口电路确定，取决于要发送的分组的可用性。 在另一个实施例中，接口电路被配置为基于链路上消耗的带宽量来动态地改变链路上的错误检测数据的传输频率。
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公开(公告)号：US07840873B2
公开(公告)日：2010-11-23
申请号：US11610219
申请日：2006-12-13
IPC分类号： H03M13/00
CPC分类号： H04L1/0061 , H04L1/0079 , H04L1/1829 , H04L2001/0097
摘要： In an embodiment, a node comprises a packet scheduler configured to schedule a packet to be transmitted on the link, the packet comprising a command and associated packet data. Coupled to the packet scheduler and configured to transmit the packet on the link, and interface circuit is configured to generate error detection data covering the packet. The interface circuit is configured to transmit the error detection data covering the packet at an end of the packet, and is further configured to insert at least one partial error detection data within the packet. The partial error detection data covers a portion of the packet that precedes the partial error detection data. A receiver is configured to receive the data and forward the data based on partial CRC check.
摘要翻译： 在一个实施例中，节点包括分组调度器，其被配置为调度要在链路上发送的分组，所述分组包括命令和相关联的分组数据。 耦合到分组调度器并且被配置为在链路上传送分组，并且接口电路被配置为生成覆盖分组的错误检测数据。 接口电路被配置为在分组的末尾发送覆盖分组的错误检测数据，并且还被配置为在分组内插入至少一个部分错误检测数据。 部分错误检测数据覆盖部分错误检测数据之前的分组的一部分。 接收机被配置为接收数据并基于部分CRC校验转发数据。
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公开(公告)号：US07881303B2
公开(公告)日：2011-02-01
申请号：US11610191
申请日：2006-12-13
CPC分类号： H04L1/0011 , H04L1/0007 , H04L1/0061 , H04L1/18
摘要： In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.
摘要翻译： 在一个实施例中，节点包括分组调度器，其被配置为调度要在链路上传送的分组以及耦合到分组调度器并被配置为在链路上传送分组的接口电路。 接口电路被配置为生成覆盖分组的错误检测数据，其中在链路上的分组之间传送错误检测数据。 接口电路被配置为通过一次错误检测数据的传输来覆盖多达N个分组，其中N是> = 2的整数。 由一个错误检测数据传输覆盖的分组的数量由接口电路确定，取决于要发送的分组的可用性。 在另一个实施例中，接口电路被配置为基于链路上消耗的带宽量来动态地改变链路上的错误检测数据的传输频率。
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公开(公告)号：US20080148131A1
公开(公告)日：2008-06-19
申请号：US11610191
申请日：2006-12-13
CPC分类号： H04L1/0011 , H04L1/0007 , H04L1/0061 , H04L1/18
摘要： In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.
摘要翻译： 在一个实施例中，节点包括分组调度器，其被配置为调度要在链路上传送的分组以及耦合到分组调度器并被配置为在链路上传送分组的接口电路。 接口电路被配置为生成覆盖分组的错误检测数据，其中在链路上的分组之间传送错误检测数据。 接口电路被配置为通过一次错误检测数据的传输来覆盖多达N个分组，其中N是> = 2的整数。 由一个错误检测数据传输覆盖的分组的数量由接口电路确定，取决于要发送的分组的可用性。 在另一个实施例中，接口电路被配置为基于链路上消耗的带宽量来动态地改变链路上的错误检测数据的传输频率。
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7.发明授权Data accessing system with an access request pipeline and access method thereof 有权具有访问请求流水线的数据访问系统及其访问方法公开(公告)号：US06718400B1
公开(公告)日：2004-04-06
申请号：US09715472
申请日：2000-11-17
申请人： Chau-Chad Tsai , Chen-Ping Yang , Chi-Che Tsai
发明人： Chau-Chad Tsai , Chen-Ping Yang , Chi-Che Tsai
IPC分类号： G06F300
CPC分类号： G06F13/161
摘要： A PCI data accessing system with a read request pipeline and an application method thereof are provided. The PCI data accessing system has a PCI master device, a memory module, and a PCI control device. The PCI master device issues a first read request, and the PCI control device converts the first read request to a second read request divided into a first part and a second part. Each part of the second request requests one line data, i.e. 64 bits data. The memory module stores data requested by the PCI master device. Moreover, there is no latency time between data for the first part and the second part returned from the memory module.
摘要翻译： 提供了具有读取请求流水线的PCI数据访问系统及其应用方法。 PCI数据访问系统具有PCI主设备，存储器模块和PCI控制设备。 PCI主设备发出第一读请求，并且PCI控制设备将第一读请求转换为分为第一部分和第二部分的第二读请求。 第二请求的每个部分请求一行数据，即64位数据。 存储器模块存储由PCI主设备请求的数据。 此外，在从存储器模块返回的第一部分和第二部分的数据之间没有等待时间。
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公开(公告)号：US20100036988A1
公开(公告)日：2010-02-11
申请号：US12187448
申请日：2008-08-07
申请人： Chien-Wei Chang , Chen-Ping Yang
发明人： Chien-Wei Chang , Chen-Ping Yang
IPC分类号： G06F13/00
摘要： A multimedia playing device includes a central processing unit, a plurality of sensors electrically coupled to the central processing unit, and an output unit electrically coupled to the central processing unit. The plurality of sensors are operated together with the central processing unit, such that after the sensors detect different hand movements of a user, the central processing unit reads and determines the hand movement and transmits related control signals to the output unit according to different hand movements to achieve the effects of using a hand posture to control related functional movements and enhancing the convenience of using the multimedia playing device.
摘要翻译： 多媒体播放设备包括中央处理单元，电耦合到中央处理单元的多个传感器，以及电耦合到中央处理单元的输出单元。 多个传感器与中央处理单元一起操作，使得在传感器检测到用户的不同的手部移动之后，中央处理单元根据不同的手部移动读取并确定手的移动并将相关的控制信号发送到输出单元 以实现使用手势来控制相关的功能运动和增强使用多媒体播放装置的便利性的效果。
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公开(公告)号：US06836829B2
公开(公告)日：2004-12-28
申请号：US09853005
申请日：2001-05-09
申请人： Chau-Chad Tsai , Chi-Che Tsai , Chen-Ping Yang
发明人： Chau-Chad Tsai , Chi-Che Tsai , Chen-Ping Yang
IPC分类号： G06F1200
CPC分类号： G06F13/4243 , G06F12/0875 , G06F2212/303
摘要： A peripheral device interface control chip having a cache system therein and a method of synchronization data transmission between the cache system and an external device in a computer system. The cache system and data synchronization method can be applied to the peripheral device interface control chip having a data buffer and a peripheral device interface controller. The data buffer is located inside the control chip for holding data stream read from a memory unit so that data required by the peripheral device is provided. When the data stream is still valid, the data stream is retained. The peripheral device interface controller is installed inside the control chip. The peripheral device interface controller detects if the data stream inside the data buffer includes the data required by the peripheral device and whether the data stream is still valid or not. The peripheral device interface controller also controls the placement of the data stream retrieved from the memory into the data buffer and state transition of the data buffer.
摘要翻译： 一种其中具有缓存系统的外围设备接口控制芯片以及在计算机系统中的高速缓存系统和外部设备之间的同步数据传输的方法。 缓存系统和数据同步方法可以应用于具有数据缓冲器和外围设备接口控制器的外围设备接口控制芯片。 数据缓冲器位于控制芯片内部，用于保持从存储器单元读取的数据流，从而提供外围设备所需的数据。 当数据流仍然有效时，保留数据流。 外围设备接口控制器安装在控制芯片内。 外围设备接口控制器检测数据缓冲器内的数据流是否包括外围设备所需的数据以及数据流是否仍然有效。 外围设备接口控制器还控制从存储器检索的数据流到数据缓冲器和数据缓冲器的状态转换的放置。
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10.发明授权Method and apparatus for arbitrating access to a PCI bus by a plurality of functions in a multi-function master 有权用于通过多功能主机中的多个功能来仲裁对PCI总线的访问的方法和装置公开(公告)号：US06546448B1
公开(公告)日：2003-04-08
申请号：US09440764
申请日：1999-11-16
申请人： Jiin Lai , Chau-Chad Tsai , Chen-Ping Yang , Chi-Che Tsai
发明人： Jiin Lai , Chau-Chad Tsai , Chen-Ping Yang , Chi-Che Tsai
IPC分类号： G06F1314
CPC分类号： G06F13/362
摘要： Method and apparatus for arbitrating access to a pci bus by a plurality of functions in a multi-function master. The arbitrating method is performed among the multiple functions of a multi-function master. The arbiter includes a rotating inquiry scheduler (RIS) and a heuristic inquiry initiator (HII). The RIS receives the local inquiry signal from the functional circuit and stores it. According to the local inquiry signal, a bus inquiry signal is generated and sent to the HII, and is sent to the PCI bus to request a use of the PCI bus. If the PCI bus responds a delay transaction termination, the HII can repeatedly send the bus inquiry signal to the PCI bus until the PCI bus grants the privilege to use the PCI bus. The HII then informs the RIS, which arranges the functional circuit to transmit data through the PCI bus.
摘要翻译： 用于通过多功能主机中的多个功能来仲裁对pci总线的访问的方法和装置。 在多功能主机的多个功能之间执行仲裁方法。 仲裁器包括旋转查询调度程序（RIS）和启发式查询启动器（HII）。 RIS从功能电路接收本地查询信号并存储。 根据本地查询信号，生成总线查询信号并将其发送到HII，并发送到PCI总线以请求使用PCI总线。 如果PCI总线响应延迟事务终止，则HII可以将总线查询信号重复发送到PCI总线，直到PCI总线授予使用PCI总线的权限。 然后，HII通知RIS，该RIS将功能电路通过PCI总线传输数据。
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