公开(公告)号：US07805567B2

公开(公告)日：2010-09-28

申请号：US11854576

申请日：2007-09-13

申请人： Chun-Yuan Su ,  Chau-Chad Tsai ,  Jiin Lai

发明人： Chun-Yuan Su ,  Chau-Chad Tsai ,  Jiin Lai

IPC分类号： G06F12/00

CPC分类号： G06F13/4027 ,  G06F11/1076 ,  G06F2211/1054

摘要： A Northbridge providing RAID access is coupled among a central processing unit, a system memory, and a Southbridge. Furthermore, the Northbridge further couples to a RAID through a Southbridge. The Northbridge include a RAID accelerator for performing RAID operations according to RAID control commands which are stored in a register.

摘要翻译： 在中央处理单元，系统存储器和南桥之间耦合提供RAID访问的北桥。 此外，北桥通过南桥进一步融合到RAID。 北桥包含RAID加速器，用于根据存储在寄存器中的RAID控制命令进行RAID操作。

公开(公告)号：US06694400B1

公开(公告)日：2004-02-17

申请号：US09451121

申请日：1999-11-30

申请人： Jiin Lai ,  Chau-Chad Tsai ,  Chen-Ping Yang ,  Sheng-Chang Peng ,  Tse-Hsien Wang

发明人： Jiin Lai ,  Chau-Chad Tsai ,  Chen-Ping Yang ,  Sheng-Chang Peng ,  Tse-Hsien Wang

IPC分类号： G06F1338

CPC分类号： G06F13/4217

摘要： A method of conducting delayed data transaction on a PCI system and its associated devices. The delayed data transaction is carried out using a PCI system to transmit data between an initiator and a responder. Both the initiator and the responder are coupled to a PCI bus. The delayed transaction in the PCI system includes a number of steps. To begin with, the initiator will send out a request to use the PCI bus so that data transmission can be conducted with respect to the responder. If the responder accepts the request but unable to secure the requested data soon enough, the responder will generate a defer identifier that corresponds to the requesting initiator. Next, a stop signal and the defer identifier generated by the responder will be returned to the initiator, indicating that the request has been accepted. When the requested data is ready in the responder, the responder will forward the defer identifier again. The initiator picks up the defer identifier and prepares according to the buffer identifier in it. Then, data transmission between the initiator and the responder begins.

摘要翻译： 在PCI系统及其相关设备上进行延迟数据交易的方法。 延迟数据事务使用PCI系统在启动器和应答器之间传输数据。 启动器和应答器都与PCI总线相连。 PCI系统中的延迟事务包括多个步骤。 首先，启动器将发出使用PCI总线的请求，以便可以对响应者进行数据传输。 如果响应者接受请求但不能足够快地保护所请求的数据，则响应者将生成对应于请求的发起者的延迟标识符。 接下来，由响应者生成的停止信号和延迟标识符将被返回给启动器，指示该请求已被接受。 当请求的数据在响应者中准备就绪时，响应者将再次转发延迟标识符。 发起人拿起延迟标识符，并根据缓冲区标识符进行准备。 然后，启动器和应答器之间的数据传输开始。

公开(公告)号：US06549964B1

公开(公告)日：2003-04-15

申请号：US09451820

申请日：1999-11-30

申请人： Jiin Lai ,  Chau-Chad Tsai ,  Chen-Ping Yang ,  Sheng-Chang Peng ,  Tse-Hsien Wang

发明人： Jiin Lai ,  Chau-Chad Tsai ,  Chen-Ping Yang ,  Sheng-Chang Peng ,  Tse-Hsien Wang

IPC分类号： G06F1300

CPC分类号： G06F13/4226

摘要： A delayed transaction method and system to handle multiple delayed transactions in a PCI system is disclosed. When the responder accepts a first and second request from an initiator but can not immediately respond to the first and second request, the responder generates a first and a second defer identifier corresponding to the initiator, respectively. When data transfer between the responder and the initiator corresponding to the first request is completed and data is ready for transfer corresponding to the second request, the responder immediately issues a second buffer identifier along with the data requested corresponding to the second request. Thus, data transfer between the initiator and the responder based on the second buffer identifier corresponding to the second request can proceed.

公开(公告)号：US20060206644A1

公开(公告)日：2006-09-14

申请号：US11433195

申请日：2006-05-11

申请人： Chau-Chad Tsai ,  Chi-Che Tsai ,  Chih-kuo Kao

发明人： Chau-Chad Tsai ,  Chi-Che Tsai ,  Chih-kuo Kao

IPC分类号： G06F13/42

CPC分类号： G06F13/423 ,  Y02D10/14 ,  Y02D10/151

摘要： The present invention provides a method of hot switching data transfer rate on the bus to hot switch the data transfer rate of the bus between the control chips without the process of RESET. When the bus between the control chips demands a large amount of data transfer, the bus is hot switched to a higher data transfer rate to fulfill the data transfer requirement. Contrarily, when the bus between the control chips demands less amount of data transfer, the bus is hot switched to a lower data transfer rate to save power consumption.

公开(公告)号：US06934789B2

公开(公告)日：2005-08-23

申请号：US09894684

申请日：2001-06-27

申请人： Sheng-Chang Peng ,  Chau-Chad Tsai ,  Hsuan-Yi Wang ,  Chi-Che Tsai

发明人： Sheng-Chang Peng ,  Chau-Chad Tsai ,  Hsuan-Yi Wang ,  Chi-Che Tsai

IPC分类号： G06F13/42 ,  G06F13/38

CPC分类号： G06F13/423

摘要： A bus data interface, structure and method for transmitting the data of a PCI bus is disclosed. The bus data interface comprises a high-bit transmitting buffer, a low-bit transmitting buffer, a multiplexer, a strobe generator, and a data distributor. The strobe generator utilizes the bus request signal and bus grant signal to transmit a data strobe signal in response to the PCI clock. According to the rising edge and falling edge of the data strobe signal, the data distributor retrieves data according to the data strobe signal. Further, the invention is compatible with the original PCI bus and allows the PCI bus to transmit data with a dual speed.

摘要翻译： 公开了一种用于发送PCI总线的数据的总线数据接口，结构和方法。 总线数据接口包括高位发送缓冲器，低位发送缓冲器，复用器，选通发生器和数据分配器。 选通发生器利用总线请求信号和总线许可信号来响应于PCI时钟发送数据选通信号。 根据数据选通信号的上升沿和下降沿，数据分配器根据数据选通信号检索数据。 此外，本发明与原始PCI总线兼容，并允许PCI总线以双速传输数据。

公开(公告)号：US06925517B2

公开(公告)日：2005-08-02

申请号：US10249361

申请日：2003-04-03

申请人： Sheng-Chang Peng ,  Chau-Chad Tsai ,  Chih-kuo Kao ,  Chi-Che Tsai

发明人： Sheng-Chang Peng ,  Chau-Chad Tsai ,  Chih-kuo Kao ,  Chi-Che Tsai

IPC分类号： H04L5/16 ,  G06F13/14 ,  G06F13/40

CPC分类号： H04L5/16

摘要： A bus for supporting plural signal line configurations and the method to switch it, used to operate in a bus between the control chips to maintain its operation flexibility. When the data transfer load in between the control chips is suitable for the bi-direction transfer, the signal line configuration of the bi-direction transfer is selected. When the direction of the bi-direction transfer switches frequently, the other signal line configuration is selected. That is, the bus signal lines are divided into two parts, each part is in charge of the data transfer in each uni-direction to avoid the turn around cycle that impacts the transfer performance.

摘要翻译： 用于支持多个信号线配置的总线及其切换方法，用于在控制芯片之间的总线中操作以保持其操作灵活性。 当控制芯片之间的数据传输负载适用于双向传输时，选择双向传输的信号线配置。 当双向传输方向频繁切换时，选择其他信号线配置。 也就是说，总线信号线分为两部分，每个部分负责每个单向的数据传输，以避免影响传输性能的转向周期。

公开(公告)号：US06795883B2

公开(公告)日：2004-09-21

申请号：US10055500

申请日：2002-01-22

申请人： Chau-Chad Tsai

发明人： Chau-Chad Tsai

IPC分类号： G06F900

CPC分类号： G06F12/0646

摘要： A method of distribution and storage for a configuration space that may be applied to an advanced computer system without modifying the BIOS or system software used in a conventional computer system. To the microprocessor, it seems that all the configuration data are still stored in the north bridge control chip. But in fact, some configuration values related to a PCI bus are stored in a south bridge control chip. The design can conceal the effect caused by quoting a high speed private bus, and meet the requirement of dividing the configuration space for the advanced system.

摘要翻译： 可以应用于高级计算机系统的配置空间的分发和存储方法，而不修改常规计算机系统中使用的BIOS或系统软件。 对于微处理器，似乎所有的配置数据仍然存储在北桥控制芯片中。 但事实上，与PCI总线相关的一些配置值存储在南桥控制芯片中。 该设计可以隐藏引用高速专用总线的效果，满足先进系统配置空间划分的要求。

公开(公告)号：US06721833B2

公开(公告)日：2004-04-13

申请号：US09735412

申请日：2000-12-12

申请人： Jiin Lai ,  Chau-Chad Tsai ,  Sheng-Chang Peng ,  Chi-Che Tsai

发明人： Jiin Lai ,  Chau-Chad Tsai ,  Sheng-Chang Peng ,  Chi-Che Tsai

IPC分类号： G06F1336

CPC分类号： G06F13/36

摘要： A bus arbitration method within a control chipset, The control chipset further comprises a first control chip and a second control chip, data are transferred between the first and the second control chips through a bus, the bus comprises a bidirectional bus The first control chip usually control the authority to use the bus, however the second control chip has higher priority to use the bus. Accompany with a bus specification without waiting cycle, to arbitrate the authority to use the bus can be done fast and without errors. Therefore, no GNT signal line is required and the arbitration time reduces.

摘要翻译： 一种控制芯片组内的总线仲裁方法，控制芯片组还包括第一控制芯片和第二控制芯片，数据通过总线在第一和第二控制芯片之间传输，总线包括双向总线第一控制芯片通常 控制使用总线的权限，但第二个控制芯片具有使用总线的优先级。 伴随总线规格无等待周期，仲裁权限使用总线可以快速，毫无错误地完成。 因此，不需要GNT信号线，仲裁时间缩短。

公开(公告)号：US06718400B1

公开(公告)日：2004-04-06

申请号：US09715472

申请日：2000-11-17

申请人： Chau-Chad Tsai ,  Chen-Ping Yang ,  Chi-Che Tsai

发明人： Chau-Chad Tsai ,  Chen-Ping Yang ,  Chi-Che Tsai

IPC分类号： G06F300

CPC分类号： G06F13/161

摘要： A PCI data accessing system with a read request pipeline and an application method thereof are provided. The PCI data accessing system has a PCI master device, a memory module, and a PCI control device. The PCI master device issues a first read request, and the PCI control device converts the first read request to a second read request divided into a first part and a second part. Each part of the second request requests one line data, i.e. 64 bits data. The memory module stores data requested by the PCI master device. Moreover, there is no latency time between data for the first part and the second part returned from the memory module.

摘要翻译： 提供了具有读取请求流水线的PCI数据访问系统及其应用方法。 PCI数据访问系统具有PCI主设备，存储器模块和PCI控制设备。 PCI主设备发出第一读请求，并且PCI控制设备将第一读请求转换为分为第一部分和第二部分的第二读请求。 第二请求的每个部分请求一行数据，即64位数据。 存储器模块存储由PCI主设备请求的数据。 此外，在从存储器模块返回的第一部分和第二部分的数据之间没有等待时间。

公开(公告)号：US06684284B1

公开(公告)日：2004-01-27

申请号：US09718811

申请日：2000-11-22

申请人： Jiin Lai ,  Chau-Chad Tsai ,  Sheng-Chang Peng ,  Chi-Che Tsai

发明人： Jiin Lai ,  Chau-Chad Tsai ,  Sheng-Chang Peng ,  Chi-Che Tsai

IPC分类号： G06F944

CPC分类号： G06F13/4027

摘要： A data transaction method between control chips. Data buffers of the control chips of the control chipset have fixed size and amount. In addition, read/write acknowledge commands are asserted in sequence according to read/write commands, by which the control chips can detect the status of the buffers within another control chips. When a control chip asserts a command, the corresponding data must be ready in advance. Therefore, the signal line for providing the waiting status, data transaction cycle and stop/retry protocol can be omitted. Accordingly, commands or data can be continuously transmitted without waiting, stop or retry, the performance is improved.

摘要翻译： 控制芯片之间的数据交易方法。 控制芯片组的控制芯片的数据缓冲器具有固定的尺寸和数量。 此外，读/写确认命令根据读/写命令依次被断言，通过该命令，控制芯片可以检测另一个控制芯片内的缓冲器的状态。 当控制芯片发出命令时，相应的数据必须提前准备就绪。 因此，可以省略用于提供等待状态，数据事务周期和停止/重试协议的信号线。 因此，可以连续发送命令或数据，而无需等待，停止或重试，提高性能。