利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

62 条记录 (耗时 0.028 秒)

    Managing multiple operating points for stable virtual frequencies
    1.
    发明授权
    Managing multiple operating points for stable virtual frequencies 有权
    为稳定的虚拟频率管理多个操作点

    公开(公告)号：US08504854B2

    公开(公告)日：2013-08-06

    申请号：US12819777

    申请日：2010-06-21

    申请人： Samuel D. Naffziger ,  John P. Petry ,  William A. Hughes

    发明人： Samuel D. Naffziger ,  John P. Petry ,  William A. Hughes

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    摘要： A system and method for managing multiple discrete operating points to create a stable virtual operating point. One or more functional blocks within a processor produces data corresponding to an activity level associated with the respective functional block. A power manager determines a power consumption value based on the data once every given sample interval. In addition, the power manager determines a signed accumulated difference over time between a thermal design power (TDP) and the power consumption value. The power manager selects a next power-performance state (P-state) based on comparisons of the signed accumulated difference and given thresholds. Transitioning between P-states in this manner while the workload does not significantly change causes the processor to operate at a virtual operating point between supported discrete operating points.

    摘要翻译： 一种用于管理多个离散工作点以创建稳定的虚拟操作点的系统和方法。 处理器内的一个或多个功能块产生对应于与相应功能块相关联的活动级别的数据。 功率管理器基于每个给定采样间隔一次的数据来确定功耗值。 此外，功率管理器确定在热设计功率（TDP）和功耗值之间随时间的经签名的积分差。 功率管理器基于签名累积差和给定阈值的比较来选择下一个功率性能状态（P状态）。 以这种方式在P状态之间转换，而工作负载不会显着变化，导致处理器在支持的离散工作点之间的虚拟工作点运行。

    Memory controller prioritization scheme
    3.
    发明授权
    Memory controller prioritization scheme 有权
    内存控制器优先级排序方案

    公开(公告)号：US07877558B2

    公开(公告)日：2011-01-25

    申请号：US11837943

    申请日：2007-08-13

    申请人： William A. Hughes ,  Vydhyanathan Kalyanasundharam ,  Philip E. Madrid ,  Roger Isaac

    发明人： William A. Hughes ,  Vydhyanathan Kalyanasundharam ,  Philip E. Madrid ,  Roger Isaac

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F13/1626

    摘要： A system includes a processor coupled to a memory through a memory controller. The memory controller includes first and second queues. The memory controller receives memory requests from the processor, assigns a priority to each request, stores each request in the first queue, and schedules processing of the requests based on their priorities. The memory controller changes the priority of a request in the first queue in response to a trigger, sends a next scheduled request from the first queue to the second queue in response to detecting the next scheduled request has the highest priority of any request in the first queue, and sends requests from the second queue to the memory. The memory controller changes the priority of different types of requests in response to different types of triggers. The memory controller maintains a copy of each request sent to the second queue in the first queue.

    摘要翻译： 系统包括通过存储器控制器耦合到存储器的处理器。 存储器控制器包括第一和第二队列。 存储器控制器从处理器接收存储器请求，为每个请求分配优先级，将每个请求存储在第一个队列中，并根据其优先级对请求进行调度处理。 存储器控制器响应于触发器改变第一队列中的请求的优先级，响应于检测到下一个调度的请求而将下一个调度的请求从第一队列发送到第二队列，该请求具有第一队列中的任何请求的最高优先级 队列，并将请求从第二个队列发送到内存。 内存控制器根据不同类型的触发器更改不同类型请求的优先级。 存储器控制器维护发送到第一队列中的第二队列的每个请求的副本。

    Shared resources in a chip multiprocessor
    4.
    发明授权
    Shared resources in a chip multiprocessor 有权
    一个芯片多处理器共享资源

    公开(公告)号：US07840780B2

    公开(公告)日：2010-11-23

    申请号：US12098303

    申请日：2008-04-04

    申请人： William A. Hughes ,  Vydhyanathan Kalyanasundharam ,  Kiran K. Bondalapati ,  Philip E. Madrid ,  Stephen C. Ennis

    发明人： William A. Hughes ,  Vydhyanathan Kalyanasundharam ,  Kiran K. Bondalapati ,  Philip E. Madrid ,  Stephen C. Ennis

    IPC分类号： G06F9/00

    CPC分类号： G06F15/8007

    摘要： In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).

    摘要翻译： 在一个实施例中，节点包括多个处理器核心和节点控制器，其被配置为接收寻址第一寄存器的第一读取操作。 节点控制器被配置为响应于第一读取操作而返回第一值，取决于哪个处理器核发送第一读取操作。 在另一个实施例中，节点包括处理器核心和节点控制器。 节点控制器包括由处理器核共享的队列。 处理器核被配置为以每N个时钟周期一个最大速率发送通信，其中N是等于处理器核心数的整数。 在另一个实施例中，节点包括处理器核和由处理器核共享的多个保险丝。 在一些实施例中，节点组件被集成到单个集成电路芯片（例如，芯片多处理器）上。

    PROCESSOR POWER MANAGEMENT AND METHOD
    5.
    发明申请
    PROCESSOR POWER MANAGEMENT AND METHOD 有权
    处理器功率管理和方法

    公开(公告)号：US20100185820A1

    公开(公告)日：2010-07-22

    申请号：US12356624

    申请日：2009-01-21

    申请人： William A. Hughes ,  Kiran K. Bondalapati ,  Vydhyanathan Kalyanasundharam ,  Kevin M. Lepak ,  Benjamin T. Sander

    发明人： William A. Hughes ,  Kiran K. Bondalapati ,  Vydhyanathan Kalyanasundharam ,  Kevin M. Lepak ,  Benjamin T. Sander

    IPC分类号： G06F1/32 ,  G06F12/08

    CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F12/0808 ,  G06F2212/1028 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D50/20

    摘要： A data processing device is disclosed that includes multiple processing cores, where each core is associated with a corresponding cache. When a processing core is placed into a first sleep mode, the data processing device initiates a first phase. If any cache probes are received at the processing core during the first phase, the cache probes are serviced. At the end of the first phase, the cache corresponding to the processing core is flushed, and subsequent cache probes are not serviced at the cache. Because it does not service the subsequent cache probes, the processing core can therefore enter another sleep mode, allowing the data processing device to conserve additional power.

    摘要翻译： 公开了一种数据处理设备，其包括多个处理核心，其中每个核心与相应的高速缓存相关联。 当处理核心被置于第一睡眠模式时，数据处理设备启动第一阶段。 如果在第一阶段期间在处理核心处接收到任何高速缓存探测器，则对缓存探测器进行服务。 在第一阶段结束时，与处理核心相对应的高速缓冲存储器被刷新，并且后续高速缓存探测器不在缓存处被服务。 因为它不服务后续的缓存探测器，因此处理核心可以进入另一个睡眠模式，从而允许数据处理设备节省额外的功率。

    APPARATUS FOR REDUCING CACHE LATENCY WHILE PRESERVING CACHE BANDWIDTH IN A CACHE SUBSYSTEM OF A PROCESSOR
    6.
    发明申请
    APPARATUS FOR REDUCING CACHE LATENCY WHILE PRESERVING CACHE BANDWIDTH IN A CACHE SUBSYSTEM OF A PROCESSOR 审中-公开
    用于在处理器的缓存子系统中保存缓存带宽时减少高速缓存的设备

    公开(公告)号：US20090006777A1

    公开(公告)日：2009-01-01

    申请号：US11769970

    申请日：2007-06-28

    申请人： Greggory D. Donley ,  William A. Hughes

    发明人： Greggory D. Donley ,  William A. Hughes

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0897 ,  G06F12/0895 ,  G06F2212/1016

    摘要： A processor cache memory subsystem includes a cache controller coupled to a tag logic unit. The cache controller may monitor read request resources associated with the cache subsystem and receive read requests for data stored in a data storage array of the cache subsystem. The tag logic unit may determine whether one or more requested address bits match any address tag stored within a tag array of the cache subsystem. The cache controller may, in response to determining the read request resources associated with the cache subsystem are available, selectably send the request for data with an implicit request indication being asserted. In response to determining the read request resources associated with the cache subsystem are not available, the cache controller may send the request for data without an implicit request indication being asserted.

    摘要翻译： 处理器高速缓存存储器子系统包括耦合到标签逻辑单元的高速缓存控制器。 高速缓存控制器可以监视与高速缓存子系统相关联的读取请求资源，并且接收对存储在高速缓存子系统的数据存储阵列中的数据的读取请求。 标签逻辑单元可以确定一个或多个所请求的地址位是否匹配存储在高速缓存子系统的标签阵列内的任何地址标签。 响应于确定与高速缓存子系统相关联的读取请求资源可用，高速缓存控制器可以可选择地发送具有被断言的隐式请求指示的数据请求。 响应于确定与高速缓存子系统相关联的读取请求资源不可用，高速缓存控制器可以发送对数据的请求，而不会隐式地请求指示。

    Shared Resources in a Chip Multiprocessor
    7.
    发明申请
    Shared Resources in a Chip Multiprocessor 有权
    芯片多处理器中的共享资源

    公开(公告)号：US20080184009A1

    公开(公告)日：2008-07-31

    申请号：US12098303

    申请日：2008-04-04

    申请人： William A. Hughes ,  Vydhyanathan Kalyanasundharam ,  Kiran K. Bondalapati ,  Philip E. Madrid ,  Stephen C. Ennis

    发明人： William A. Hughes ,  Vydhyanathan Kalyanasundharam ,  Kiran K. Bondalapati ,  Philip E. Madrid ,  Stephen C. Ennis

    IPC分类号： G06F15/76 ,  G06F9/30

    CPC分类号： G06F15/8007

    摘要： In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).

    摘要翻译： 在一个实施例中，节点包括多个处理器核心和节点控制器，其被配置为接收寻址第一寄存器的第一读取操作。 节点控制器被配置为响应于第一读取操作而返回第一值，取决于哪个处理器核发送第一读取操作。 在另一个实施例中，节点包括处理器核心和节点控制器。 节点控制器包括由处理器核共享的队列。 处理器核被配置为以每N个时钟周期一个最大速率发送通信，其中N是等于处理器核心数的整数。 在另一个实施例中，节点包括处理器核和由处理器核共享的多个保险丝。 在一些实施例中，节点组件被集成到单个集成电路芯片（例如，芯片多处理器）上。

    Core redundancy in a chip multiprocessor for highly reliable systems
    8.
    发明授权
    Core redundancy in a chip multiprocessor for highly reliable systems 有权
    用于高可靠性系统的芯片多处理器的核心冗余

    公开(公告)号：US07328371B1

    公开(公告)日：2008-02-05

    申请号：US10966466

    申请日：2004-10-15

    申请人： Vydhyanathan Kalyanasundharam ,  William A. Hughes ,  Philip E. Madrid ,  Scott A. White ,  Ajay Naini

    发明人： Vydhyanathan Kalyanasundharam ,  William A. Hughes ,  Philip E. Madrid ,  Scott A. White ,  Ajay Naini

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1641 ,  G06F11/1679 ,  G06F11/181 ,  G06F11/184 ,  G06F2201/845

    摘要： In one embodiment, a node comprises a plurality of processor cores and a node controller coupled to the processor cores. The node controller is configured to route communications from the processor cores to other devices in a computer system. The node controller comprises a circuit coupled to receive the communications from the processor cores. In a redundant execution mode in which at least a first processor core is redundantly executing code that a second processor core is also executing, the circuit is configured to compare communications from the first processor core to communications from the second processor core to verify correct execution of the code. In some embodiments, the processor cores and the node controller may be integrated onto a single integrated circuit chip as a CMP. A similar method is also contemplated.

    摘要翻译： 在一个实施例中，节点包括多个处理器核和耦合到处理器核的节点控制器。 节点控制器被配置为将来自处理器核心的通信路由到计算机系统中的其他设备。 节点控制器包括耦合以从处理器核心接收通信的电路。 在冗余执行模式中，其中至少第一处理器核冗余地执行第二处理器核也正在执行的代码，该电路被配置为将来自第一处理器核心的通信与来自第二处理器核心的通信进行比较，以验证是否正确执行 代码。 在一些实施例中，处理器核心和节点控制器可以作为CMP集成到单个集成电路芯片上。 也可以考虑类似的方法。

    Combined system responses in a chip multiprocessor
    9.
    发明授权
    Combined system responses in a chip multiprocessor 有权
    芯片多处理器中的组合系统响应

    公开(公告)号：US07296167B1

    公开(公告)日：2007-11-13

    申请号：US10956537

    申请日：2004-10-01

    申请人： William A. Hughes

    发明人： William A. Hughes

    IPC分类号： G06F1/26 ,  G06F12/08

    CPC分类号： G06F1/3203 ,  G06F12/0831

    摘要： In one embodiment, a node comprises, integrated onto a single integrated circuit chip (in some embodiments), a plurality of processor cores and a node controller coupled to the plurality of processor cores. The node controller is coupled to receive an external request transmitted to the node, and is configured to transmit a corresponding request to at least a subset of the plurality of processor cores responsive to the external request. The node controller is configured to receive respective responses from each processor core of the subset. Each processor core transmits the respective response independently in response to servicing the corresponding request and is capable of transmitting the response on different clock cycles than other processor cores. The node controller is configured to transmit an external response to the external request responsive to receiving each of the respective responses.

    摘要翻译： 在一个实施例中，节点包括集成到单个集成电路芯片（在一些实施例中），多个处理器核和耦合到多个处理器核的节点控制器。 节点控制器被耦合以接收发送到节点的外部请求，并且被配置为响应于外部请求向多个处理器核心的至少一个子集发送相应的请求。 节点控制器被配置为从子集的每个处理器核心接收相应的响应。 每个处理器核心响应于对相应请求的服务而独立地发送相应的响应，并且能够在不同于其它处理器核心的时钟周期上发送响应。 节点控制器被配置为响应于接收每个相应的响应而向外部请求发送外部响应。