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公开(公告)号：US07362697B2
公开(公告)日：2008-04-22
申请号：US10339757
申请日：2003-01-09
申请人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
发明人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
IPC分类号： G01R31/08
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.
摘要翻译： 一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。 检测用于芯片的信号路径集合内的有缺陷的信号路径。 信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径 有缺陷的信号路径。
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公开(公告)号：US20110010482A1
公开(公告)日：2011-01-13
申请号：US12886404
申请日：2010-09-20
申请人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
发明人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
IPC分类号： G06F13/00
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.
摘要翻译： 一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。 检测用于芯片的信号路径集合内的有缺陷的信号路径。 信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径 有缺陷的信号路径。
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公开(公告)号：US07813266B2
公开(公告)日：2010-10-12
申请号：US11948620
申请日：2007-11-30
申请人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
发明人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
IPC分类号： G01R31/08
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.
摘要翻译： 一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。 检测用于芯片的信号路径集合内的有缺陷的信号路径。 信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径 有缺陷的信号路径。
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公开(公告)号：US20100085872A1
公开(公告)日：2010-04-08
申请号：US12635121
申请日：2009-12-10
申请人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
发明人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
IPC分类号： H04L12/26
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.
摘要翻译： 一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。 检测用于芯片的信号路径集合内的有缺陷的信号路径。 信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径 有缺陷的信号路径。
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公开(公告)号：US07233170B2
公开(公告)日：2007-06-19
申请号：US11211955
申请日：2005-08-25
申请人： Wiren Dale Becker , Anand Haridass , Bao G. Truong
发明人： Wiren Dale Becker , Anand Haridass , Bao G. Truong
IPC分类号： H03K19/00
CPC分类号： H03K5/00 , H03K5/135 , H04L25/0276
摘要： Data busses are configured as N differential channels driven by a data signal and its complement through two off-chip drivers (OCDs). Each OCD is preceded by a programmable delay element and a two way MUX. The two data channels either transmit the data signals or a common clock signal as determined by a select signal from a skew controller. The differential signals are received in a differential receiver and a phase detector. The output of the phase detector in each differential channel is routed through an N×1 MUX. The N×1 MUX is controlled by the skew controller. The output of the N×1 MUX is fed back as a phase error feedback signal to the skew controller. Each differential data channel is sequentially selected and the programmable delays are adjusted until the phase error feedback signal from the selected phase detector reaches a predetermined minimum allowable value. Periodic adjustment may be implemented for calibration.
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6.发明申请公开(公告)号：US20080175327A1
公开(公告)日：2008-07-24
申请号：US12058689
申请日：2008-03-29
IPC分类号： H04B3/00
CPC分类号： H04L25/45
摘要： A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
摘要翻译： 使用频率F的第一时钟信号用于使用主/从触发器（FF）将数据耦合到片外驱动器（OCD），其中主锁存器由第一时钟信号计时，从锁存器以 第一个时钟信号的补码。 从第一时钟信号产生频率为F / 2的第二时钟信号。 第二时钟信号被移位等于第一时钟信号的周期的大致一半的时间。 在一个实施例中，使用延迟线电路来移位第二时钟。 在另一个实施例中，使用主/从FF来移位第二时钟，其中主锁存器用第一时钟信号的补码进行计时，从锁存器用第一时钟信号计时。 传播时钟的边缘之间的数据的逻辑状态转换，从而减少与时钟转换的耦合，从而减少边缘抖动。
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7.发明授权公开(公告)号：US07477068B2
公开(公告)日：2009-01-13
申请号：US12058689
申请日：2008-03-29
IPC分类号： H03K17/16
CPC分类号： H04L25/45
摘要： A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
摘要翻译： 使用频率F的第一时钟信号用于使用主/从触发器（FF）将数据耦合到片外驱动器（OCD），其中主锁存器由第一时钟信号计时，从锁存器以 第一个时钟信号的补码。 从第一时钟信号产生频率为F / 2的第二时钟信号。 第二时钟信号被移位等于第一时钟信号的周期的大致一半的时间。 在一个实施例中，使用延迟线电路来移位第二时钟。 在另一个实施例中，使用主/从FF来移位第二时钟，其中主锁存器用第一时钟信号的补码进行计时，从锁存器用第一时钟信号计时。 传播时钟的边缘之间的数据的逻辑状态转换，从而减少与时钟转换的耦合，从而减少边缘抖动。
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8.发明授权公开(公告)号：US07382151B1
公开(公告)日：2008-06-03
申请号：US11611200
申请日：2006-12-15
IPC分类号： H03K17/16
CPC分类号： H04L25/45
摘要： A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
摘要翻译： 使用频率F的第一时钟信号用于使用主/从触发器（FF）将数据耦合到片外驱动器（OCD），其中主锁存器由第一时钟信号计时，从锁存器以 第一个时钟信号的补码。 从第一时钟信号产生频率为F / 2的第二时钟信号。 第二时钟信号被移位等于第一时钟信号的周期的大致一半的时间。 在一个实施例中，使用延迟线电路来移位第二时钟。 在另一个实施例中，使用主/从FF来移位第二时钟，其中主锁存器用第一时钟信号的补码进行计时，从锁存器用第一时钟信号计时。 传播时钟的边缘之间的数据的逻辑状态转换，从而减少与时钟转换的耦合，从而减少边缘抖动。
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9.发明申请公开(公告)号：US20080143375A1
公开(公告)日：2008-06-19
申请号：US11611200
申请日：2006-12-15
IPC分类号： H03K19/00 , H03K19/003
CPC分类号： H04L25/45
摘要： A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
摘要翻译： 使用频率F的第一时钟信号用于使用主/从触发器（FF）将数据耦合到片外驱动器（OCD），其中主锁存器由第一时钟信号计时，从锁存器以 第一个时钟信号的补码。 从第一时钟信号产生频率为F / 2的第二时钟信号。 第二时钟信号被移位等于第一时钟信号的周期的大致一半的时间。 在一个实施例中，使用延迟线电路来移位第二时钟。 在另一个实施例中，使用主/从FF来移位第二时钟，其中主锁存器用第一时钟信号的补码进行计时，从锁存器用第一时钟信号计时。 传播时钟的边缘之间的数据的逻辑状态转换，从而减少与时钟转换的耦合，从而减少边缘抖动。
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10.发明授权Boundary scannable one bit precompensated CMOS driver with compensating pulse width control 失效边界可扫描一位预补偿CMOS驱动器，具有补偿脉宽控制公开(公告)号：US06772250B2
公开(公告)日：2004-08-03
申请号：US09810058
申请日：2001-03-15
IPC分类号： G06F1300
CPC分类号： G06F13/4077 , H03K19/00346 , H03K19/017581
摘要： An improved data driver, method, and system for driving data with an improved slew rate and eye opening is provided. In one embodiment, the data driver includes a non-precompensating data driver and a precompensating data driver. The non-precompensating driver generates a non-precompensating output data pulse corresponding to input data. The non-precompensating data driver generates a pulse in response to every input data bit received. The precompensating driver generates the precompensating pulse only in response to a transition from one data state to a second data state between consecutive data bits. The precompensating data pulse is shorter in duration than the non-precompensating output data. The output data from the data drive is the sum of the non-precompensating output data pulse and the precompensating output data pulse.
摘要翻译： 提供了一种改进的数据驱动程序，方法和系统，用于驱动具有改进的压摆率和眼睛开度的数据。 在一个实施例中，数据驱动器包括非预补偿数据驱动器和预补偿数据驱动器。 非预补偿驱动器产生对应于输入数据的非预补偿输出数据脉冲。 非预补偿数据驱动器响应于接收的每个输入数据位产生脉冲。 预补偿驱动器仅响应于在连续数据位之间从一个数据状态到第二数据状态的转变而产生预补偿脉冲。 预补偿数据脉冲的持续时间比非预补偿输出数据短。 来自数据驱动器的输出数据是非预补偿输出数据脉冲和预补偿输出数据脉冲之和。
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