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42 条记录 (耗时 0.017 秒)

    Programmable driver delay
    1.
    发明授权
    Programmable driver delay 有权

    公开(公告)号：US07233170B2

    公开(公告)日：2007-06-19

    申请号：US11211955

    申请日：2005-08-25

    申请人： Wiren Dale Becker ,  Anand Haridass ,  Bao G. Truong

    发明人： Wiren Dale Becker ,  Anand Haridass ,  Bao G. Truong

    IPC分类号： H03K19/00

    CPC分类号： H03K5/00 ,  H03K5/135 ,  H04L25/0276

    摘要： Data busses are configured as N differential channels driven by a data signal and its complement through two off-chip drivers (OCDs). Each OCD is preceded by a programmable delay element and a two way MUX. The two data channels either transmit the data signals or a common clock signal as determined by a select signal from a skew controller. The differential signals are received in a differential receiver and a phase detector. The output of the phase detector in each differential channel is routed through an N×1 MUX. The N×1 MUX is controlled by the skew controller. The output of the N×1 MUX is fed back as a phase error feedback signal to the skew controller. Each differential data channel is sequentially selected and the programmable delays are adjusted until the phase error feedback signal from the selected phase detector reaches a predetermined minimum allowable value. Periodic adjustment may be implemented for calibration.

    Differential transmitter circuit
    4.
    发明授权
    Differential transmitter circuit 有权
    差分发射电路

    公开(公告)号：US07512183B2

    公开(公告)日：2009-03-31

    申请号：US11086718

    申请日：2005-03-22

    申请人： Anand Haridass ,  Bao G. Truong ,  Joel D. Ziegelbein

    发明人： Anand Haridass ,  Bao G. Truong ,  Joel D. Ziegelbein

    IPC分类号： H04B3/00

    CPC分类号： H04L25/0274 ,  H03F3/45197 ,  H03F2200/543 ,  H03F2203/45488

    摘要： A driver circuit is configured as a frequency compensated differential amplifier having one input coupled to a first data signal and a second input coupled to a second data signal. Each stage of the differential amplifier is biased with a current source. The driver circuit generates a first output signal coupled to the input of a first transmission line and a second output signal coupled to the input of a second transmission line. The first and second output signals are generated as the difference between the first and second data signals amplified by a compensated gain. A compensation network that attenuates the low frequency components of the input signals relative to the high frequency components is coupled between current sources biasing the differential amplifier. The outputs of the first and second transmission lines are coupled to the inputs of a differential receiver that may or may not be frequency compensated.

    摘要翻译： 驱动器电路被配置为具有耦合到第一数据信号的一个输入和耦合到第二数据信号的第二输入的频率补偿差分放大器。 差分放大器的每个级都用电流源偏置。 驱动器电路产生耦合到第一传输线的输入的第一输出信号和耦合到第二传输线的输入的第二输出信号。 第一和第二输出信号被产生为由补偿增益放大的第一和第二数据信号之间的差。 相对于高频分量衰减输入信号的低频分量的补偿网络耦合在偏置差分放大器的电流源之间。 第一和第二传输线的输出耦合到差分接收机的输入端，该差分接收机可以被频率补偿也可以不被频率补偿。

    SYSTEM FOR REDUCING CROSS-TALK INDUCED SOURCE SYNCHRONOUS BUS CLOCK JITTER
    6.
    发明申请
    SYSTEM FOR REDUCING CROSS-TALK INDUCED SOURCE SYNCHRONOUS BUS CLOCK JITTER 有权
    用于减少交叉输入源同步总线时钟抖动器的系统

    公开(公告)号：US20080175327A1

    公开(公告)日：2008-07-24

    申请号：US12058689

    申请日：2008-03-29

    申请人： Bao G. Truong ,  Daniel Mark Dreps ,  Anand Haridass ,  John C. Schiff ,  Joel D. Ziegelbein

    发明人： Bao G. Truong ,  Daniel Mark Dreps ,  Anand Haridass ,  John C. Schiff ,  Joel D. Ziegelbein

    IPC分类号： H04B3/00

    CPC分类号： H04L25/45

    摘要： A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.

    摘要翻译： 使用频率F的第一时钟信号用于使用主/从触发器（FF）将数据耦合到片外驱动器（OCD），其中主锁存器由第一时钟信号计时，从锁存器以 第一个时钟信号的补码。 从第一时钟信号产生频率为F / 2的第二时钟信号。 第二时钟信号被移位等于第一时钟信号的周期的大致一半的时间。 在一个实施例中，使用延迟线电路来移位第二时钟。 在另一个实施例中，使用主/从FF来移位第二时钟，其中主锁存器用第一时钟信号的补码进行计时，从锁存器用第一时钟信号计时。 传播时钟的边缘之间的数据的逻辑状态转换，从而减少与时钟转换的耦合，从而减少边缘抖动。

    Mitigate Power Supply Noise Response by Throttling Execution Units Based Upon Voltage Sensing
    7.
    发明申请
    Mitigate Power Supply Noise Response by Throttling Execution Units Based Upon Voltage Sensing 失效
    通过基于电压检测的截止执行单元来缓解电源噪声响应

    公开(公告)号：US20070283172A1

    公开(公告)日：2007-12-06

    申请号：US11420820

    申请日：2006-05-30

    申请人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

    发明人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

    IPC分类号： G06F1/00

    CPC分类号： G06F1/26

    摘要： A system for mitigating power supply and power distribution system noise response by throttling execution units based upon voltage sensing in a circuit is provided. A sensing unit senses the voltage of a circuit. The sensing unit determines if the execution of another execution unit will cause the circuit voltage to drop below a threshold level. In response to a determination that the execution of another execution unit will cause the circuit voltage to drop below the threshold level, the execution unit is throttled.

    摘要翻译： 提供了一种通过基于电路中的电压感测的节流执行单元来减轻电源和配电系统噪声响应的系统。 感测单元感测电路的电压。 感测单元确定另一个执行单元的执行是否会导致电路电压降至阈值以下。 响应于确定另一执行单元的执行将导致电路电压降低到阈值水平以下，执行单元被调节。

    Circuit for generating a tracking reference voltage
    8.
    发明授权
    Circuit for generating a tracking reference voltage 失效
    用于产生跟踪参考电压的电路

    公开(公告)号：US07208972B2

    公开(公告)日：2007-04-24

    申请号：US10845568

    申请日：2004-05-13

    申请人： Daniel M. Dreps ,  Anand Haridass ,  Bao G. Truong

    发明人： Daniel M. Dreps ,  Anand Haridass ,  Bao G. Truong

    IPC分类号： H03K17/16

    CPC分类号： H04L25/061 ,  H04L25/45

    摘要： Two or more integrated circuit (IC) chips are separated by a significant distance relative to their communication frequency such that pseudo-differential signaling is used to improve signal detection. A derived reference voltage is generated that tracks the variations of the driver and receiver side power supply variations that normally reduce noise margins. The derived reference voltage is filtered to reduce high frequency response and coupled as the reference to differential receivers used to detect the logic levels of the communication signals.

    摘要翻译： 两个或多个集成电路（IC）芯片相对于它们的通信频率被隔开相当长的距离，使得伪差分信号用于改善信号检测。 产生导出的参考电压，其跟踪通常降低噪声容限的驱动器和接收机侧电源变化的变化。 导出的参考电压被滤波以降低高频响应并作为用于检测通信信号的逻辑电平的差分接收器的参考而耦合。

    Apparatus and method for selectively monitoring multiple voltages in an IC or other electronic chip
    9.
    发明授权
    Apparatus and method for selectively monitoring multiple voltages in an IC or other electronic chip 失效
    用于选择性地监测IC或其他电子芯片中的多个电压的装置和方法

    公开(公告)号：US07469199B2

    公开(公告)日：2008-12-23

    申请号：US11278848

    申请日：2006-04-06

    申请人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

    发明人： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

    IPC分类号： G06F11/00

    CPC分类号： G01R19/16552

    摘要： An apparatus and method are provided for monitoring the voltage available in each domain of multiple voltage domains of a partitioned electronic chip. The apparatus comprises a single conductive link coupled to the chip, and further comprises a domain selection network having a single output and a plurality of switchable inputs, the output being connected to the single conductive link, and two inputs being connected to monitor respective voltage levels of two of the plurality of voltage domains. A control mechanism is disposed to operate the selection network, in order to selectively connect one of the inputs to the single conductive link, and a sensor device external to the electronic chip is connected to measure the monitored respective voltage levels of two of the plurality of voltage domains using the single conductive link.

    摘要翻译： 提供了一种用于监视分区电子芯片的多个电压域的每个域中可用电压的装置和方法。 该装置包括耦合到芯片的单个导电链路，并且还包括具有单个输出和多个可切换输入的域选择网络，该输出连接到单个导电链路，并且两个输入端被连接以监视相应的电压电平 的多个电压域中的两个。 设置控制机构以操作选择网络，以便选择性地将输入中的一个连接到单个导电链路，并且连接到电子芯片外部的传感器装置以测量所监测的多个 电压域使用单个导电链路。