公开(公告)号：US11832035B2

公开(公告)日：2023-11-28

申请号：US17232207

申请日：2021-04-16

Applicant: XILINX, INC.

Inventor： Aman Gupta ,  Sagheer Ahmad ,  Ygal Arbel ,  Abbas Morshed ,  Eun Mi Kim

IPC: H04Q3/00 ,  G06F13/16 ,  G06F13/40

CPC classification number: H04Q3/0004 ,  G06F13/1668 ,  G06F13/4027

Abstract: Embodiments herein describe an integrated circuit that includes a NoC with at least two levels of switching: a sparse network and a non-blocking network. In one embodiment, the non-blocking network is a localized interconnect that provides an interface between the sparse network in the NoC and a memory system that requires additional bandwidth such as HBM2/3 or DDR5. Hardware elements connected to the NoC that do not need the additional benefits provided by the non-blocking network can connect solely to the sparse network. In this manner, the NoC provides a sparse network (which has a lower density of switching elements) for providing communication between lower bandwidth hardware elements and a localized non-blocking network for facilitating communication between the sparse network and higher bandwidth hardware elements.

公开(公告)号：US11714779B2

公开(公告)日：2023-08-01

申请号：US16830142

申请日：2020-03-25

Applicant: XILINX, INC.

Inventor： Abbas Morshed ,  Ygal Arbel ,  Eun Mi Kim

IPC: G06F15/78 ,  G06F5/10 ,  G06F9/38 ,  G06F13/40

CPC classification number: G06F15/7825 ,  G06F5/10 ,  G06F9/38 ,  G06F13/4027 ,  G06F2205/064 ,  G06F2213/0038

Abstract: Embodiments herein describe a SoC that includes a NoC that supports both strict and relax ordering requests. That is, some applications may require strict ordering where requests transmitted from the same ingress logic to different egress logic blocks are performed sequentially. However, other applications may not require strict ordering, such as interleaved writes to memory. In those applications, relax ordering can be used were the same ingress logic block can transmit multiple requests to different egress logic blocks in parallel. For example, an ingress logic block may receive a first request that is indicated as being a relaxed ordered request. After transmitting the request to an egress logic block, the ingress logic block may receive a second request. The ingress logic block can transmit the second request to a different egress logic block without waiting for a response for the first request.