公开(公告)号：US08694939B1

公开(公告)日：2014-04-08

申请号：US13802181

申请日：2013-03-13

Applicant: Xilinx, Inc.

Inventor： Alan M. Frost ,  Matthew H. Klein ,  Ronald L. Cline

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F2217/84

Abstract: A method for determining a critical junction temperature for a user-design implemented in a field programmable gate array (programmable device), includes: obtaining a static power vs. temperature curve for the user-design implemented in the programmable device; obtaining a system thermal curve for the user-design implemented in the programmable device; and using the static power vs. temperature curve for the user-design implemented in the programmable device and the system thermal curve for the user-design implemented in the programmable device to determine the critical junction temperature.

Abstract translation: 用于确定在现场可编程门阵列（可编程器件）中实现的用户设计的关键结温度的方法包括：获得在可编程器件中实现的用户设计的静态功率对温度曲线; 获得在可编程设备中实现的用户设计的系统热曲线; 并使用在可编程器件中实现的用户设计的静态功率与温度曲线以及在可编程器件中实现的用户设计的系统热曲线来确定临界结温度。

公开(公告)号：US09529946B1

公开(公告)日：2016-12-27

申请号：US13676035

申请日：2012-11-13

Applicant: Xilinx, Inc.

Inventor： Paul R. Schumacher ,  Graham F. Schelle ,  Patrick Lysaght ,  Alan M. Frost

IPC: G06F17/50 ,  G06F11/26

CPC classification number: G06F17/5022 ,  G06F11/00 ,  G06F11/261 ,  G06F11/3062 ,  G06F11/3457 ,  G06F17/5027

Abstract: An integrated circuit can include a processor operable to execute program code and an Intellectual Property (IP) modeling block. The IP modeling block can include a first port through which the IP modeling block receives first modeling data and a second port coupled to the processor through which the first IP modeling block communicates with the processor during emulation. The first IP modeling block also can include a power emulation circuit. The power emulation circuit is configured to consume a variable amount of power as specified by the first modeling data received via the first port.

Abstract translation: 集成电路可以包括可操作以执行程序代码和知识产权（IP）建模块的处理器。 IP建模块可以包括第一端口，IP建模块通过该第一端口接收第一建模数据，以及耦合到处理器的第二端口，第一IP建模块在仿真期间与处理器通信。 第一个IP建模块还可以包括一个电源仿真电路。 功率仿真电路被配置为消耗由经由第一端口接收的第一建模数据指定的可变量的功率。

公开(公告)号：US09268898B1

公开(公告)日：2016-02-23

申请号：US13797810

申请日：2013-03-12

Applicant: Xilinx, Inc.

Inventor： Alan M. Frost ,  Matthew H. Klein

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/78

Abstract: Estimating power consumption of a circuit design includes associating, using a processor, each partition of a plurality of partitions of a circuit design with a probability distribution (315). For each partition, the associated probability distribution specifies a distribution for a probability distribution parameter correlated with power consumption for the partition. Using the processor, an output probability distribution specifying power consumption of the circuit design can be calculated according to the probability distribution of each partition of the circuit design (320).

Abstract translation: 估计电路设计的功耗包括使用处理器将电路设计的多个分区的每个分区与概率分布相关联（315）。 对于每个分区，相关联的概率分布指定与分区的功耗相关的概率分布参数的分布。 使用处理器，可以根据电路设计的每个分区的概率分布来计算指定电路设计的功耗的输出概率分布（320）。