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公开(公告)号：US10474610B1
公开(公告)日：2019-11-12
申请号：US15676530
申请日：2017-08-14
Applicant: Xilinx, Inc.
Inventor： Graham F. Schelle , Patrick Lysaght , Yun Qu , Parimal Patel
Abstract: An integrated circuit can include programmable circuitry configured to implement an overlay circuit specified by an overlay. The overlay circuit can include a trace buffer configured to receive a probed signal from circuitry within the overlay circuit. The trace buffer can be configured to generate trace data from the probed signal and store the trace data in a runtime allocated memory. The integrated circuit also can include a processor coupled to the programmable circuitry and configured to control operation of the trace buffer. The processor can be configured to read the trace data from the runtime allocated memory.
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公开(公告)号：US09846449B1
公开(公告)日：2017-12-19
申请号：US14322411
申请日：2014-07-02
Applicant: Xilinx, Inc.
Inventor： Paul R. Schumacher , Graham F. Schelle , Bradley K. Fross
Abstract: An integrated circuit including a universal monitor system includes a detector circuit. The detector circuit includes a start trigger circuit receiving first signals, an end trigger circuit receiving second signals, and a latency circuit coupled to outputs of the start and end trigger circuits. The start trigger circuit detects a start event from the first signals. The end trigger circuit detects an end event from the second signals. The detector circuit further includes: a data trigger circuit receiving third signals and detecting transferred data therefrom; a first counter circuit coupled to the latency circuit and calculating a total latency; a second counter circuit coupled to at least one of the start trigger circuit and counting start events, or the end trigger circuit and counting end events; and a third counter circuit coupled to an output of the data trigger circuit and counting a total amount of data transferred.
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公开(公告)号：US09678150B2
公开(公告)日：2017-06-13
申请号：US14924090
申请日：2015-10-27
Applicant: Xilinx, Inc.
Inventor： Graham F. Schelle , Yi-Hua E. Yang , Philip B. James-Roxby , Paul R. Schumacher , Patrick Lysaght
IPC: G06F11/22 , G06F17/50 , G01R31/317 , G01R31/3177
CPC classification number: G01R31/31703 , G01R31/3177 , G06F17/5022
Abstract: Various example implementations are directed to circuits and methods for debugging circuit designs. According to an example implementation, waveform data is captured, for a set of signals produced by a circuit design during operation. Data structures are generated for the set of signals and waveform data for the signals is stored in the data structures. Communication channels associated with the set of signals are identified. Waveform data stored in the data structures is analyzed to locate transaction-level events in the set of signal for one or more communication channels. Data indicating locations of the set of transaction-level events is output by the computer system.
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公开(公告)号：US10430200B2
公开(公告)日：2019-10-01
申请号：US15676453
申请日：2017-08-14
Applicant: Xilinx, Inc.
Inventor： Patrick Lysaght , Graham F. Schelle , Parimal Patel , Peter K. Ogden
Abstract: An integrated circuit can include a slave processor configured to execute instructions. The slave processor can be implemented in programmable circuitry of the integrated circuit. The integrated circuit also can include a processor coupled to the slave processor. The processor can be hardwired and configured to control operation of the slave processor.
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公开(公告)号：US20170115348A1
公开(公告)日：2017-04-27
申请号：US14924090
申请日：2015-10-27
Applicant: Xilinx, Inc.
Inventor： Graham F. Schelle , Yi-Hua E. Yang , Philip B. James-Roxby , Paul R. Schumacher , Patrick Lysaght
IPC: G01R31/317 , G01R31/3177
CPC classification number: G01R31/31703 , G01R31/3177 , G06F17/5022
Abstract: Various example implementations are directed to circuits and methods for debugging circuit designs. According to an example implementation, waveform data is captured, for a set of signals produced by a circuit design during operation. Data structures are generated for the set of signals and waveform data for the signals is stored in the data structures. Communication channels associated with the set of signals are identified. Waveform data stored in the data structures is analyzed to locate transaction-level events in the set of signal for one or more communication channels. Data indicating locations of the set of transaction-level events is output by the computer system.
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Patent Agency Ranking
公开(公告)号：US09608871B1
公开(公告)日：2017-03-28
申请号：US14280211
申请日：2014-05-16
Applicant: Xilinx, Inc.
Inventor： Paul R. Schumacher , Graham F. Schelle
IPC: G06F17/50 , H04L12/24 , G06F3/0484
CPC classification number: G06F3/04842 , G06F17/50 , H04L41/14 , H04L41/145 , H04L43/50
Abstract: Performance analysis for an electronic system includes determining, using a processor, data traffic patterns stored within a core library of an electronic design automation system, wherein the data traffic patterns are part of cores stored within the core library. The determined data traffic patterns are displayed using a display as modeling options. A user input selecting a displayed data traffic pattern is received; and the selected data traffic pattern is executed as part of modeling the electronic system.
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公开(公告)号：US09348619B1
公开(公告)日：2016-05-24
申请号：US13797721
申请日：2013-03-12
Applicant: Xilinx, Inc.
Inventor： Patrick Lysaght , Paul R. Schumacher , Graham F. Schelle , Yi-Hua Yang
CPC classification number: G06F9/455 , G06F17/5027
Abstract: A user interface is provided for selection of a previously specified scenario from a plurality of previously specified scenarios. Each previously specified scenario includes a previously specified topology of the electronic system, one or more previously specified parameter values applied to the electronic system, a previously specified traffic profile, and respective precompiled values of one or more measurands. In response to user selection of one of the previously specified scenarios, the precompiled values of the measurands are displayed. The user interface further provides for specification of a scenario. In response to user specification of a scenario, traffic emulation circuitry in the programmable IC is configured to execute the scenario. The value of the at least one measurand is computed and displayed.
Abstract translation: 提供用户界面用于从多个先前指定的场景中选择先前指定的场景。 每个先前指定的方案包括电子系统的先前指定的拓扑，应用于电子系统的一个或多个先前指定的参数值，先前指定的流量简档，以及一个或多个被测量的相应预编译值。 响应于用户选择之前指定的方案之一，显示被测量的预编译值。 用户界面还提供了场景的规范。 响应于场景的用户指定，可编程IC中的业务仿真电路被配置为执行该场景。 计算并显示至少一个被测量的值。
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公开(公告)号：US09977758B1
公开(公告)日：2018-05-22
申请号：US14887080
申请日：2015-10-19
Applicant: Xilinx, Inc.
Inventor： Paul R. Schumacher , Kumar Deepak , Graham F. Schelle
CPC classification number: G06F13/4221 , G06F2212/1016 , G06F2212/1024
Abstract: A system may include a first region implemented in programmable circuitry of a programmable integrated circuit. The first region may include predefined interface circuitry configured to communicate with a host processor. The system may include a second region implemented in the programmable circuitry of the programmable integrated circuit. The second region may include a first hardware accelerated kernel of an OpenCL application. The system may include a first monitor circuit implemented within the first region or the second region. The first hardware accelerated kernel and the first monitor circuit may be coupled to the interface circuitry of the first region. The first monitor circuit may be operable responsive to control signals received from the host processor of a platform through the interface circuitry to store operation data for the first region or the first hardware accelerated kernel.
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公开(公告)号：US09846587B1
公开(公告)日：2017-12-19
申请号：US14278263
申请日：2014-05-15
Applicant: Xilinx, Inc.
Inventor： Paul R. Schumacher , Graham F. Schelle , Patrick Lysaght , Yi-Hua Yang
IPC: G06F9/455
Abstract: A system includes a host data processing system and a target platform coupled to the host data processing system. The target platform includes an emulation system. The emulation system includes a processor system, an emulation circuit coupled to the processor system through an integrated circuit (IC) interconnect, and a performance monitor coupled to the IC interconnect. The emulation system receives, from the host data processing system, a software emulation model and a data traffic pattern. The emulation system emulates a system architecture by executing the software emulation model within the processor system and implementing the data traffic pattern over the IC interconnect using the emulation circuit. The emulation system provides, to the host data processing system, measurement data collected by the performance monitor during the emulation.
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公开(公告)号：US09626780B1
公开(公告)日：2017-04-18
申请号：US14312616
申请日：2014-06-23
Applicant: Xilinx, Inc.
Inventor： Yi-Hua E. Yang , Patrick Lysaght , Paul R. Schumacher , Graham F. Schelle
IPC: G06T11/20
CPC classification number: G06T11/206 , G06T11/203
Abstract: Visualizing transactions in a transaction-based system includes displaying, on a display device, an x-y coordinate system including an x-axis and a y-axis, wherein the x-axis is demarcated in units of time and the y-axis is demarcated according to a transaction characteristic and formatting, using a processor, each of a plurality of transactions of a transaction system as a line having a start end representing a start of the transaction and a terminating end representing an end of the transaction. For each line representing a transaction, the start end of the line is located at a first x-coordinate corresponding to a start time of the transaction and a first y-coordinate of zero. For each line, the terminating end of the line is located at a second x-coordinate corresponding to an end time of the transaction and a second non-zero y-coordinate that is the same for each line. Each line is displayed on the display device using the processor in combination with the x-y coordinate system.
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