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    Device profiling for tuning OpenCL applications on programmable integrated circuits
    1.
    发明授权
    Device profiling for tuning OpenCL applications on programmable integrated circuits 有权

    公开(公告)号：US09977758B1

    公开(公告)日：2018-05-22

    申请号：US14887080

    申请日：2015-10-19

    Applicant: Xilinx, Inc.

    Inventor： Paul R. Schumacher ,  Kumar Deepak ,  Graham F. Schelle

    IPC: G06F13/42 ,  G06F9/445

    CPC classification number: G06F13/4221 ,  G06F2212/1016 ,  G06F2212/1024

    Abstract: A system may include a first region implemented in programmable circuitry of a programmable integrated circuit. The first region may include predefined interface circuitry configured to communicate with a host processor. The system may include a second region implemented in the programmable circuitry of the programmable integrated circuit. The second region may include a first hardware accelerated kernel of an OpenCL application. The system may include a first monitor circuit implemented within the first region or the second region. The first hardware accelerated kernel and the first monitor circuit may be coupled to the interface circuitry of the first region. The first monitor circuit may be operable responsive to control signals received from the host processor of a platform through the interface circuitry to store operation data for the first region or the first hardware accelerated kernel.

    Performance analysis using configurable hardware emulation within an integrated circuit
    2.
    发明授权
    Performance analysis using configurable hardware emulation within an integrated circuit 有权

    公开(公告)号：US09846587B1

    公开(公告)日：2017-12-19

    申请号：US14278263

    申请日：2014-05-15

    Applicant: Xilinx, Inc.

    Inventor： Paul R. Schumacher ,  Graham F. Schelle ,  Patrick Lysaght ,  Yi-Hua Yang

    IPC: G06F9/455

    CPC classification number: G06F9/455 ,  G06F11/34 ,  G06F17/50

    Abstract: A system includes a host data processing system and a target platform coupled to the host data processing system. The target platform includes an emulation system. The emulation system includes a processor system, an emulation circuit coupled to the processor system through an integrated circuit (IC) interconnect, and a performance monitor coupled to the IC interconnect. The emulation system receives, from the host data processing system, a software emulation model and a data traffic pattern. The emulation system emulates a system architecture by executing the software emulation model within the processor system and implementing the data traffic pattern over the IC interconnect using the emulation circuit. The emulation system provides, to the host data processing system, measurement data collected by the performance monitor during the emulation.

    Visualizing transactions of a transaction-based system
    3.
    发明授权
    Visualizing transactions of a transaction-based system 有权

    公开(公告)号：US09626780B1

    公开(公告)日：2017-04-18

    申请号：US14312616

    申请日：2014-06-23

    Applicant: Xilinx, Inc.

    Inventor： Yi-Hua E. Yang ,  Patrick Lysaght ,  Paul R. Schumacher ,  Graham F. Schelle

    IPC: G06T11/20

    CPC classification number: G06T11/206 ,  G06T11/203

    Abstract: Visualizing transactions in a transaction-based system includes displaying, on a display device, an x-y coordinate system including an x-axis and a y-axis, wherein the x-axis is demarcated in units of time and the y-axis is demarcated according to a transaction characteristic and formatting, using a processor, each of a plurality of transactions of a transaction system as a line having a start end representing a start of the transaction and a terminating end representing an end of the transaction. For each line representing a transaction, the start end of the line is located at a first x-coordinate corresponding to a start time of the transaction and a first y-coordinate of zero. For each line, the terminating end of the line is located at a second x-coordinate corresponding to an end time of the transaction and a second non-zero y-coordinate that is the same for each line. Each line is displayed on the display device using the processor in combination with the x-y coordinate system.

    Integrated circuit pre-boot metadata transfer
    4.
    发明授权
    Integrated circuit pre-boot metadata transfer 有权
    集成电路预引导元数据传输

    公开(公告)号：US09323876B1

    公开(公告)日：2016-04-26

    申请号：US14552321

    申请日：2014-11-24

    Applicant: Xilinx, Inc.

    Inventor： Patrick Lysaght ,  Yi-Hua E. Yang ,  Paul R. Schumacher ,  Graham F. Schelle

    IPC: G06F17/50 ,  G06F9/445

    CPC classification number: G06F8/65 ,  G06F17/5054

    Abstract: Pre-boot metadata transfer may include loading a first configuration bitstream into a programmable integrated circuit (IC), wherein the first configuration bitstream includes a first circuit design and metadata for a second circuit design. The metadata may be stored within a memory of the programmable IC. A configuration bitstream load condition may be detected and, responsive to the configuration bitstream load condition, a second configuration bitstream may be loaded into the programmable IC. The second configuration bitstream includes a second circuit design.

    Abstract translation: 预引导元数据传输可以包括将第一配置比特流加载到可编程集成电路（IC）中，其中第一配置比特流包括用于第二电路设计的第一电路设计和元数据。 元数据可以存储在可编程IC的存储器中。 可以检测配置比特流加载条件，并且响应于配置比特流加载条件，可以将第二配置比特流加载到可编程IC中。 第二配置比特流包括第二电路设计。

    Interactive datasheet system
    7.
    发明授权
    Interactive datasheet system 有权
    交互式数据表系统

    公开(公告)号：US09348619B1

    公开(公告)日：2016-05-24

    申请号：US13797721

    申请日：2013-03-12

    Applicant: Xilinx, Inc.

    Inventor： Patrick Lysaght ,  Paul R. Schumacher ,  Graham F. Schelle ,  Yi-Hua Yang

    IPC: G06G7/62 ,  G06F9/455

    CPC classification number: G06F9/455 ,  G06F17/5027

    Abstract: A user interface is provided for selection of a previously specified scenario from a plurality of previously specified scenarios. Each previously specified scenario includes a previously specified topology of the electronic system, one or more previously specified parameter values applied to the electronic system, a previously specified traffic profile, and respective precompiled values of one or more measurands. In response to user selection of one of the previously specified scenarios, the precompiled values of the measurands are displayed. The user interface further provides for specification of a scenario. In response to user specification of a scenario, traffic emulation circuitry in the programmable IC is configured to execute the scenario. The value of the at least one measurand is computed and displayed.

    Abstract translation: 提供用户界面用于从多个先前指定的场景中选择先前指定的场景。 每个先前指定的方案包括电子系统的先前指定的拓扑，应用于电子系统的一个或多个先前指定的参数值，先前指定的流量简档，以及一个或多个被测量的相应预编译值。 响应于用户选择之前指定的方案之一，显示被测量的预编译值。 用户界面还提供了场景的规范。 响应于场景的用户指定，可编程IC中的业务仿真电路被配置为执行该场景。 计算并显示至少一个被测量的值。

    High-throughput regular expression processing with capture using an integrated circuit
    8.
    发明授权
    High-throughput regular expression processing with capture using an integrated circuit 有权

    公开(公告)号：US11861171B2

    公开(公告)日：2024-01-02

    申请号：US17660808

    申请日：2022-04-26

    Applicant: Xilinx, Inc.

    Inventor： Sachin Kumawat ,  David K. Liddell ,  Paul R. Schumacher

    IPC: G06F3/06

    CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0673

    Abstract: A system includes a first multi-port RAM storing an instruction table. The instruction table specifies a regular expression for application to a data stream and a second multi-port RAM configured to store a capture table having capture entries decodable for tracking position information for a sequence of characters matching a capture sub-expression of the regular expression. The system includes a regular expression engine processing the data stream to determine match states by tracking active states for the regular expression and priorities for the active states by storing the active states of the regular expression in a plurality of priority FIFO memories in decreasing priority order. The system includes a capture engine operating in coordination with the regular expression engine to determine character(s) of the data stream that match the capture sub-expression based on the active state being tracked and decoding the capture entries of the capture table.

    HIGH-THROUGHPUT REGULAR EXPRESSION PROCESSING WITH CAPTURE USING AN INTEGRATED CIRCUIT
    9.
    发明公开
    HIGH-THROUGHPUT REGULAR EXPRESSION PROCESSING WITH CAPTURE USING AN INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20230342030A1

    公开(公告)日：2023-10-26

    申请号：US17660808

    申请日：2022-04-26

    Applicant: Xilinx, Inc.

    Inventor： Sachin Kumawat ,  David K. Liddell ,  Paul R. Schumacher

    IPC: G06F3/06

    CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0673

    Abstract: A system includes a first multi-port RAM storing an instruction table. The instruction table specifies a regular expression for application to a data stream and a second multi-port RAM configured to store a capture table having capture entries decodable for tracking position information for a sequence of characters matching a capture sub-expression of the regular expression. The system includes a regular expression engine processing the data stream to determine match states by tracking active states for the regular expression and priorities for the active states by storing the active states of the regular expression in a plurality of priority FIFO memories in decreasing priority order. The system includes a capture engine operating in coordination with the regular expression engine to determine character(s) of the data stream that match the capture sub-expression based on the active state being tracked and decoding the capture entries of the capture table.

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