公开(公告)号：US10713403B1

公开(公告)日：2020-07-14

申请号：US16374494

申请日：2019-04-03

Applicant: Xilinx, Inc.

Inventor： Shreegopal S. Agrawal ,  Jaipal R. Nareddy ,  Suman Kumar Timmireddy ,  Benjamin D. Curry ,  Siddharth Rele ,  Sozon Panou

IPC: G06F30/30 ,  G06F30/20 ,  G06F30/31 ,  G06F30/327 ,  G06F30/323

Abstract: Apparatus and associated methods relate to controlling synthesis of an electronic design by tagging an intellectual property (IP) parameter such that changes to the tagged design parameter do not result in the entire electronic design being re-synthesized. In an illustrative example, a circuit may contain a number of hard blocks, which may be configured using an HDL design tool. Whenever an IP parameter of an HDL design is updated, place and route may go out of date, which may require the entire design to be re-synthesized. By tagging certain IP parameters with at least one tag, changes or alterations to these tagged IP parameters will not cause synthesis to occur (for output products associated with the at least one tag). Avoiding re-synthesis may save significant time for designers by performing re-synthesis only when necessary.