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公开(公告)号:US10713403B1
公开(公告)日:2020-07-14
申请号:US16374494
申请日:2019-04-03
Applicant: Xilinx, Inc.
Inventor: Shreegopal S. Agrawal , Jaipal R. Nareddy , Suman Kumar Timmireddy , Benjamin D. Curry , Siddharth Rele , Sozon Panou
IPC: G06F30/30 , G06F30/20 , G06F30/31 , G06F30/327 , G06F30/323
Abstract: Apparatus and associated methods relate to controlling synthesis of an electronic design by tagging an intellectual property (IP) parameter such that changes to the tagged design parameter do not result in the entire electronic design being re-synthesized. In an illustrative example, a circuit may contain a number of hard blocks, which may be configured using an HDL design tool. Whenever an IP parameter of an HDL design is updated, place and route may go out of date, which may require the entire design to be re-synthesized. By tagging certain IP parameters with at least one tag, changes or alterations to these tagged IP parameters will not cause synthesis to occur (for output products associated with the at least one tag). Avoiding re-synthesis may save significant time for designers by performing re-synthesis only when necessary.
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公开(公告)号:US10289785B1
公开(公告)日:2019-05-14
申请号:US15266963
申请日:2016-09-15
Applicant: Xilinx, Inc.
Inventor: Sozon Panou
Abstract: Creating a platform architecture can include receiving, using a computer, user input specifying a plurality of attributes of the platform architecture, wherein the platform architecture is adapted for implementation in a system-on-chip, and determining, based on the attributes and using the computer, a processing domain of the platform architecture, wherein the processing domain includes a processor, a software operating context, a device, and a memory. A hardware description of the platform architecture is generated using the computer. The hardware description specifies the processing domain, wherein the operating context is adapted for execution by the processor, and the device and the memory are addressable by the processor.
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